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公开(公告)号:AU2020298425A2
公开(公告)日:2022-01-06
申请号:AU2020298425
申请日:2020-06-15
Applicant: PANASONIC IP CORP AMERICA
Inventor: TOMA TADAMASA , NISHI TAKAHIRO , ABE KIYOFUMI , KATO YUSUKE
IPC: H04N19/577
Abstract: A coding device (100) is provided with a circuit and a memory connected to the circuit. The circuit in operation: derives, as a first parameter, a sum of a plurality of horizontal gradient sum absolute values respectively derived with respect to a plurality of relative pixel positions; derives, as a second parameter, a sum of a plurality of vertical gradient sum absolute values respectively derived with respect to the plurality of relative pixel positions; derives, as a third parameter, a sum of a plurality of horizontally corresponding pixel difference values respectively derived with respect to the plurality of relative pixel positions; derives, as a fourth parameter, a sum of a plurality of vertically corresponding pixel difference values respectively derived with respect to the plurality of relative pixel positions; derives, as a fifth parameter, a sum of a plurality of vertically corresponding horizontal gradient sums respectively derived with respect to the plurality of relative pixel positions; and, using the first parameter, the second parameter, the third parameter, the fourth parameter, and the fifth parameter, generates a prediction image for use in coding of a current block.
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公开(公告)号:AU2020298425A1
公开(公告)日:2021-12-23
申请号:AU2020298425
申请日:2020-06-15
Applicant: PANASONIC IP CORP AMERICA
Inventor: TOMA TADAMASA , NISHI TAKAHIRO , ABE KIYOFUMI , KATO YUSUKE
IPC: H04N19/577
Abstract: A coding device (100) is provided with a circuit and a memory connected to the circuit. The circuit in operation: derives, as a first parameter, a sum of a plurality of horizontal gradient sum absolute values respectively derived with respect to a plurality of relative pixel positions; derives, as a second parameter, a sum of a plurality of vertical gradient sum absolute values respectively derived with respect to the plurality of relative pixel positions; derives, as a third parameter, a sum of a plurality of horizontally corresponding pixel difference values respectively derived with respect to the plurality of relative pixel positions; derives, as a fourth parameter, a sum of a plurality of vertically corresponding pixel difference values respectively derived with respect to the plurality of relative pixel positions; derives, as a fifth parameter, a sum of a plurality of vertically corresponding horizontal gradient sums respectively derived with respect to the plurality of relative pixel positions; and, using the first parameter, the second parameter, the third parameter, the fourth parameter, and the fifth parameter, generates a prediction image for use in coding of a current block.
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公开(公告)号:HUE053955T2
公开(公告)日:2021-08-30
申请号:HUE19160699
申请日:2003-04-16
Applicant: PANASONIC IP CORP AMERICA
Inventor: KONDO SATOSHI , KADONO SHINYA , HAGAI MAKOTO , ABE KIYOFUMI
IPC: H04N19/51 , H04N19/52 , G06T9/00 , H04N7/12 , H04N7/26 , H04N7/36 , H04N7/46 , H04N7/50 , H04N19/103 , H04N19/105 , H04N19/109 , H04N19/127 , H04N19/137 , H04N19/176 , H04N19/503 , H04N19/61 , H04N19/70
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公开(公告)号:HUE052192T2
公开(公告)日:2021-04-28
申请号:HUE18211538
申请日:2003-02-26
Applicant: PANASONIC IP CORP AMERICA
Inventor: KONDO SATOSHI , KADONO SHINYA , HAGAI MAKOTO , ABE KIYOFUMI
IPC: H04N19/102 , G06T9/00 , H03M7/36 , H04N19/105 , H04N19/109 , H04N19/114 , H04N19/137 , H04N19/139 , H04N19/16 , H04N19/176 , H04N19/196 , H04N19/423 , H04N19/44 , H04N19/46 , H04N19/50 , H04N19/51 , H04N19/577 , H04N19/58 , H04N19/70 , H04N19/91
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公开(公告)号:CA3119646A1
公开(公告)日:2020-07-09
申请号:CA3119646
申请日:2019-12-23
Applicant: PANASONIC IP CORP AMERICA
Inventor: LIM CHONG SOON , SUN HAI WEI , TEO HAN BOON , LI JING YA , KUO CHE-WEI , ABE KIYOFUMI , TOMA TADAMASA , NICHI TAKAHIRO , KATO YUSUKE
IPC: H04N19/117
Abstract: A coding device (100) that codes coding target blocks of an image is provided with a processor (a1) and memory (a2) that is connected to the processor (a1). The processor (a1) generates, for a motion, a first predicted image having an integer pixel unit on the basis of a motion vector, and uses an interpolation filter to interpolate the values of the minimum pixel positions between a plurality of integer pixels included in the first predicted image, thereby generating a second predicted image, and, on the basis of the second predicted image, codes coding target blocks. Usage of the interpolation filter involves switching between a first interpolation filter and a second interpolation filter in which the number of taps differs from the first interpolation filter.
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公开(公告)号:CA3105938A1
公开(公告)日:2020-01-23
申请号:CA3105938
申请日:2019-07-05
Applicant: PANASONIC IP CORP AMERICA
Inventor: LI JING YA , LIM CHONG SOON , SHASHIDHAR SUGHOSH PAVAN , LIAO RU LING , SUN HAI WEI , TEO HAN BOON , ABE KIYOFUMI , TOMA TADAMASA , NISHI TAKAHIRO
IPC: H04N19/52
Abstract: A coding device (100) is provided with a circuit (160) and a memory (162) connected to the circuit (160). The circuit (160): selects, from a plurality of tables which are used, during an operation, to correct a reference motion vector into a predetermined direction using a correction value designated by an index, and which have correction values with respectively different intervals between indexes, a first table used for a partition to be coded of an image in a moving image; writes a parameter indicating a first index to be selected from among indexes included in the first table; and codes the partition using the reference motion vector corrected by means of a correction value designated by the first index.
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公开(公告)号:HUE044739T2
公开(公告)日:2019-11-28
申请号:HUE17204573
申请日:2003-04-16
Applicant: PANASONIC IP CORP AMERICA
Inventor: KONDO SATOSHI , KADONO SHINYA , HAGAI MAKOTO , ABE KIYOFUMI
IPC: H04N19/51 , G06T9/00 , H04N7/12 , H04N7/26 , H04N7/36 , H04N7/46 , H04N7/50 , H04N19/103 , H04N19/105 , H04N19/109 , H04N19/127 , H04N19/137 , H04N19/176 , H04N19/503 , H04N19/61 , H04N19/70
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公开(公告)号:CA3157007A1
公开(公告)日:2019-11-28
申请号:CA3157007
申请日:2019-05-09
Applicant: PANASONIC IP CORP AMERICA
Inventor: TOMA TADAMASA , NISHI TAKAHIRO , ABE KIYOFUMI , KANOH RYUICHI , LIM CHONG SOON , SHASHIDHAR SUGHOSH PAVAN , LIAO RU LING , SUN HAI WEI , TEO HAN BOON , LI JING YA
Abstract: An encoder partitions into blocks using a set of block partition modes obtained by combining one or more block partition modes defining a partition type. The set of block partition modes includes a first partition mode defining the partition direction and number of partitions for partitioning a first block, and a second block partition mode defining the partition direction and number of partitions for partitioning a second block which is one of blocks obtained after the first block is partitioned. When the number of partitions of the first block partition mode is three, the second block is a center block among the blocks obtained after partitioning the first block, and the partition direction of the second block partition mode is same as the partition direction of the first block partition mode, the second block partition mode includes only a block partition mode indicating that the number of partitions is three.
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公开(公告)号:CA3093204A1
公开(公告)日:2019-09-12
申请号:CA3093204
申请日:2019-03-04
Applicant: PANASONIC IP CORP AMERICA
Inventor: SHASHIDHAR SUGHOSH PAVAN , SUN HAI WEI , LIM CHONG SOON , LIAO RU LING , TEO HAN BOON , LI JING YA , NISHI TAKAHIRO , ABE KIYOFUMI , KANOH RYUICHI , TOMA TADAMASA
IPC: H04N19/119 , H04N19/157 , H04N19/176
Abstract: A coding device (100) for coding a block to be coded included in a picture is provided with a circuit and a memory. The circuit divides the block to be coded into a first sub-block, a second sub-block, and a third sub-block in a first direction using the memory, the second sub-block being located between the first sub-block and the third sub-block, prohibits the second sub-block from being divided into two partitions in the first direction, and codes the first sub-block, the second sub-block, and the third sub-block.
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公开(公告)号:CA3069579A1
公开(公告)日:2019-01-17
申请号:CA3069579
申请日:2018-07-11
Applicant: PANASONIC IP CORP AMERICA
Inventor: OHKAWA MASATO , SAITOU HIDEO , TOMA TADAMASA , NISHI TAKAHIRO , ABE KIYOFUMI , KANOH RYUICHI
IPC: H04N19/124
Abstract: A coding device (100) for coding a block to be coded of a picture is provided with a circuit and a memory, wherein the circuit generates a first transformation coefficient using the memory by performing a first transformation on a residual signal of the block to be coded using a first transformation base, generates a second transformation coefficient by performing a second transformation on the first transformation coefficient using a second transformation base when the first transformation base matches a predetermined transformation base, quantizes the second transformation coefficient, and quantizes the first transformation coefficient without performing the second transformation when the first transformation base differs from the predetermined transformation base.
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