公开(公告)号：JPH0982982A

公开(公告)日：1997-03-28

申请号：JP26500295

申请日：1995-09-19

Applicant: SONY CORP

Inventor： KUNII MASABUMI

IPC: H01L27/08 ,  H01L21/336 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide the passivation structure of a bottom gate type thin-film transistor capable of reducing damage applied by ion doping and hydrogenation treatment. SOLUTION: A thin-film transistor has bottom gate structure, and has a gate electrode 2, a gate insulating film 3 and an active layer 4a successively superposed on an insulating substrate 1 from a lower section and a source region 6S/a drain region 6D adjacent to the active layer 4a. The active layer 4a mainly comprises unsingle crystal silicon. A silicon dioxide thin-film 8 for passivation is formed while being brought into contact with the active layer 4a and/or the source region 6S/the drain region 6D. A silicon nitride thin-film 9 is further shaped onto the thin-film 8. Damage, etc., by ion doping can be inhibited by directly bringing the silicon dioxide thin-film 8 into contact with the active layer 4a and the source region 6S/the drain region 6D and using the thin-film 8 as a passivation layer.

公开(公告)号：JPH095791A

公开(公告)日：1997-01-10

申请号：JP17420795

申请日：1995-06-16

Applicant: SONY CORP

Inventor： URAZONO TAKENOBU ,  HAYASHI HISAO ,  INO MASUMITSU ,  KUNII MASABUMI ,  NISHIHARA SHIZUO

IPC: G02F1/136 ,  G02F1/1368 ,  G09F9/30 ,  H01L21/225 ,  H01L21/268 ,  H01L21/336 ,  H01L29/786

Abstract: PURPOSE: To uniformly and efficiently introduce impurities into semiconductor thin films with a low-temp. treatment. CONSTITUTION: The first semiconductor thin film 2, a gate insulating film 3 and the second semiconductor thin film 4 are successively formed on a transparent insulating substrate 1. Plural transistors(TRs) are integrated and formed by working these semiconductor thin films 2, 4. The semiconductor device for display is formed by integrating and forming pixel electrodes 11 connected to the respective TRs. At this time, diffusion source films 5 contg. the impurities are deposited in direct superposition on the respective semiconductor thin films 2, 4. The impurities are diffused from the diffusion source films 5 into the semiconductor thin films 2, 4 by integral irradiation with a laser beam so as to include the plural TRs.

公开(公告)号：JPH0864836A

公开(公告)日：1996-03-08

申请号：JP22258794

申请日：1994-08-24

Applicant: SONY CORP

Inventor： KUNII MASABUMI ,  INO MASUMITSU ,  URAZONO TAKENOBU ,  NISHIHARA SHIZUO ,  HAYASHI HISAO

IPC: H01L21/20 ,  H01L21/02 ,  H01L21/265 ,  H01L21/268 ,  H01L21/336 ,  H01L27/12 ,  H01L29/786

Abstract: PURPOSE: To stably radiate the laser beam to a semiconductor thin film crystalizing the semiconductor, and at the same time and activate impurity. CONSTITUTION: First, a semiconductor thin film 2 is formed on an insulating substrate 1 in a film forming process. Next, a series of processings are performed, as the fabrication process, to many element regions specified on a semiconductor thin film 2 to form many thin film transistors. In this case, at the intermediate stage of the series of processings, the laser beam is radiated, as the radiation process for crystalizing the semiconductor thin film 2 under the condition that semiconductor thin film 2 is provided continuously for many element regions. This radiation process is carried out after the impurity implantation to the semiconductor thin film 2 for crystallization of the semiconductor thin film 2 included in the channel part (ch) and simultaneously for activating impurity implanted to the source region S and drain region D.

公开(公告)号：JPH0786609A

公开(公告)日：1995-03-31

申请号：JP25261993

申请日：1993-09-14

Applicant: SONY CORP

Inventor： KUNII MASABUMI

IPC: G02F1/136 ,  G02F1/1368 ,  H01L29/78 ,  H01L29/786

Abstract: PURPOSE:To control the threshold voltage of a multi-gate semiconductor element arbitrarily after the completion of the element by mutually connecting the drain regions and source regions of adjacent thin-film transistors by an impurity region patterned in a specified shape and controlling the potential of the impurity region. CONSTITUTION:One multi-gate semiconductor element has a structure in which a plurality of TFTs are connected, and formed in the so-called double gate type. A common gate line GL is formed by a pattern so as to cross a pair of a source region S1 and a drain region D1 and a pair of a source region S2 and a drain region D2, thus constituting thin-film transistors TFT1, TFT2. A plurality of the multi-gate semiconductor elements 2 are connected mutually by a common control line CL. An adjusting means 3 Is connected to the control line CL, and the neutral point potential of each multi-gate semiconductor element 2 is controlled, thus adjusting the threshold potential of a plurality of the multi- gate semiconductor elements 2 in common.

公开(公告)号：JPH06265940A

公开(公告)日：1994-09-22

申请号：JP26155593

申请日：1993-09-24

Applicant: SONY CORP

Inventor： KUNII MASABUMI ,  HAYASHI YUJI

IPC: G02F1/133 ,  G02F1/136 ,  G02F1/1368 ,  H01L21/336 ,  H01L29/78 ,  H01L29/786 ,  H01L29/784

Abstract: PURPOSE:To suppress the variations in gate capacitance coupling and to shorten a channel length by suppressing the leak current of TFTs to be used as pixel switching element, thereby stabilizing the threshold voltage. CONSTITUTION:The switching element has a multigate structure formed by serially connecting plural pieces of the thin-film transistors(TFTs) and electrically connecting respective gate electrodes 9 to each other. The TFTs have the LDD structure provided with low-concn. impurity regions 6 of the same conduction type as the conduction type of source regions or drain regions between at least source regions 3 or drain regions 5 and channel regions 2. At least one piece of plural pieces of the low-concn. impurity regions are formed to the length or concn. different from the length or concn. of the others in some cases, by which sufficient on-currents are assured while leak currents are suppressed.

公开(公告)号：JP2010147269A

公开(公告)日：2010-07-01

申请号：JP2008323363

申请日：2008-12-19

Applicant: Sony Corp ,  ソニー株式会社

Inventor： KUNII MASABUMI

IPC: H01L21/336 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a thin-film semiconductor device for forming a gate insulating film formed of a high-quality silicon oxide nitride film on a large-sized substrate. SOLUTION: In the method of manufacturing the thin-film semiconductor device, a parallel flat plate type plasma CVD apparatus is used to form the silicon nitride oxide film used as the gate insulating film 5; the nitrogen monoxide (N 2 O) gas and silane gas (SiH 4 ) are used as the film forming gas; and the flow rate of the nitrogen monoxide (N 2 O) gas for the flow rate of silane gas (SiH 4 ) is set to 2.5 or greater. The gate insulating film 5 may be formed as a laminated film, in combination with a silicon nitride film. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 解决的问题：提供一种制造用于在大尺寸基板上形成由优质氧化硅氮化物膜形成的栅极绝缘膜的薄膜半导体器件的方法。 解决方案：在制造薄膜半导体器件的方法中，使用平行平板型等离子体CVD装置形成用作栅极绝缘膜5的氮氧化硅膜; 使用一氧化氮（N 2 O）气体和硅烷气体（SiH 4 ）作为成膜气体; 对于硅烷气体流量（SiH 4 ），一氧化氮（N 2 O）气体的流量设定为2.5以上。 栅绝缘膜5可以与氮化硅膜组合形成为层叠膜。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2009157349A

公开(公告)日：2009-07-16

申请号：JP2008269590

申请日：2008-10-20

Applicant: Sony Corp ,  ソニー株式会社

Inventor： INO MASUMITSU ,  TANAKA TSUTOMU ,  ITO RYOICHI ,  KUNII MASABUMI ,  IKEDA HIROYUKI ,  IKEDA MASANOBU

IPC: G02F1/135 ,  G02F1/133 ,  G02F1/13357 ,  G09F9/00 ,  G09F9/30

CPC classification number: G02F1/1362 ,  G02F1/13338 ,  G02F2001/13312 ,  G02F2201/58 ,  G09G3/3406 ,  G09G2320/0626 ,  G09G2360/144 ,  G09G2360/148

Abstract: PROBLEM TO BE SOLVED: To achieve improvement of image quality and position detecting accuracy in a display device. SOLUTION: Operation of a backlight 300 which outputs illuminating light from the side of one surface of a liquid crystal panel 200 to a display region PA is controlled based on light reception data obtained by an external light sensor element 32b. The operation of the backlight 300 is controlled based on the light reception data obtained by the external light sensor element 32b arranged in the display region PA. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：为了实现显示装置中的图像质量和位置检测精度的提高。 解决方案：基于由外部光传感器元件32b获得的光接收数据来控制从液晶面板200的一个表面的侧面向显示区域PA输出照明光的背光源300的操作。 基于由布置在显示区域PA中的外部光传感器元件32b获得的光接收数据来控制背光300的操作。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2007306022A

公开(公告)日：2007-11-22

申请号：JP2007183391

申请日：2007-07-12

Applicant: Sony Corp ,  ソニー株式会社

Inventor： NOGUCHI TAKASHI ,  USUI SETSUO ,  KANETANI YASUHIRO ,  KUNII MASABUMI ,  IKEDA YUJI

IPC: H01L21/20 ,  H01L21/336 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a silicon thin film which allows silicon monocrystal particle assemblages with less particle diameter variation to be regularly placed on a base substance. SOLUTION: A silicon thin film contains a silicon monocrystal particle assemblage with approximate rectangular silicon monocrystal particles placed in matrix on a base substance. In addition, more than 30% in the quantity of silicon monocrystal particles constituting the silicon monocrystal particle assemblage have ä100} aspects for the base substance surface and its average film thickness is 1×10 -8 m or 4×10 -8 m. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种硅薄膜，其允许具有较小粒径变化的硅单晶颗粒组合被规则地放置在基础物质上。 解决方案：硅薄膜包含硅单晶颗粒组合，其具有矩阵放置在基体上的近似矩形硅单晶颗粒。 此外，构成硅单晶粒子组合物的硅单晶粒子的量的30％以上对于基体物质表面具有ä100}方面，其平均膜厚度为1×10 -8 m或4 ×10 -8 米。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2005039026A

公开(公告)日：2005-02-10

申请号：JP2003273910

申请日：2003-07-14

Applicant: Sony Corp ,  ソニー株式会社

Inventor： KUNII MASABUMI

IPC: H01L21/20 ,  H01L21/322 ,  H01L21/336 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a thin film transistor which can assure a threshold voltage without depending upon conductivity type even when processing of a semiconductor thin film is performed by steam annealing, and to provide the thin film transistor.
SOLUTION: The method for manufacturing the thin film transistor includes a step of forming the semiconductor thin film 34 on a substrate 31 via silicon nitride film 32 and a silicon oxide film 33, and high pressure steam annealing the semiconductor thin film 34 as its heat treatment in a moisture atmosphere. The method further includes a step of removing a spontaneous oxide film on a surface of the semiconductor thin film 34 as needed, and then patterning the semiconductor thin film 34. Thereafter, the method includes a step of forming a gate insulating film 35 in a state of covering directly the front surface of the semiconductor thin film 34, and forming the gate electrode on the gate insulating film 35. Then, the method includes a step of ion implanting phosphorus (P
+ ) as group V impurity in the semiconductor thin film 34 via the gate insulating film 35.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 解决的问题：提供一种薄膜晶体管的制造方法，即使在通过蒸汽退火进行半导体薄膜的处理的情况下也可以确保阈值电压而不依赖于导电型，并且提供薄膜晶体管 。 解决方案：薄膜晶体管的制造方法包括：通过氮化硅膜32和氧化硅膜33在基板31上形成半导体薄膜34的步骤，将半导体薄膜34进行高压蒸汽退火，如 其在潮湿环境中的热处理。 该方法还包括根据需要去除半导体薄膜34的表面上的自发氧化膜，然后对半导体薄膜34进行图案化的步骤。此后，该方法包括以下状态形成栅极绝缘膜35的步骤 直接覆盖半导体薄膜34的前表面，并在栅绝缘膜35上形成栅电极。然后，该方法包括离子注入磷（P + ）作为V族的步骤 通过栅极绝缘膜35在半导体薄膜34中的杂质。（C）2005，JPO＆NCIPI

公开(公告)号：JP2003188182A

公开(公告)日：2003-07-04

申请号：JP2001383601

申请日：2001-12-17

Applicant: SONY CORP

Inventor： KUNII MASABUMI

IPC: G02F1/1368 ,  G09F9/00 ,  G09F9/30 ,  G09F9/35 ,  H01L21/316 ,  H01L21/336 ,  H01L27/32 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a method for fabricating a thin film transistor exhibiting a good mobility in which a high quality oxide film is formed on a low melting point glass substrate while suppressing contraction thereof and to realize a high performance thin film transistor. SOLUTION: The method for fabricating a thin film transistor having a multilayer structure of a semiconductor thin film, an oxide film and a gate electrode comprises a step for forming a semiconductor thin film of polysilicon on an insulating substrate, and a step for forming an oxide film on the semiconductor thin film, wherein the step for forming an oxide film conducts a step for forming a silicon oxide film on the semiconductor thin film in combination with a first annealing step performing heat treatment in the pressure atmosphere of a gas containing oxygen atoms, and a second annealing step performing a heat treatment in a dry atmosphere is conducted following the first annealing step. COPYRIGHT: (C)2003,JPO