-
公开(公告)号：JPH10191392A
公开(公告)日：1998-07-21
申请号：JP4447197
申请日：1997-02-27
Applicant: SONY CORP
Inventor： KANO MAMORU , KUROKAWA MASUYOSHI , IWASE SEIICHIRO , NAKAMURA KENICHIRO
Abstract: PROBLEM TO BE SOLVED: To attain pixel number transformation in an optional ratio that corresponds to an optional chroma format and a scan line number. SOLUTION: A SIMD controlled linear array type multi parallel processor 1 is used, and pixel number transformation processing in an optional ratio is performed with only software processing. At this time, in the case of 4:4:4 format, same pixel number transformation is respectively performed for luminance and chroma. In the case of 4:2:2 format, cubic interpolation is performed for a luminance signal and linear interpolation is performed for a chroma signal and the pixel number transformation is performed. Or it is transformed into 4:4:4 format and the same pixel number transformation is performed. In the case of 4:1:1: format, it is transformed into 4:2:2 format and the same pixel number transformation processing is performed. Or 4:2:2 format into which is transformed is further transformed into 4:4:4 format and the same pixel number transformation processing is performed.
-
公开(公告)号：JPH10133618A
公开(公告)日：1998-05-22
申请号：JP28710496
申请日：1996-10-29
Applicant: SONY CORP
Inventor： KANO MAMORU , KUROKAWA MASUYOSHI , NAKAMURA KENICHIRO , IWASE SEIICHIRO
Abstract: PROBLEM TO BE SOLVED: To realize the number-of-pixel conversion and number-of-scanning line conversion of an arbitrary rate and to deal with change of bit accuracy, addition of new format specification or the like after designing. SOLUTION: Each element processor 10 has a local memory 15 storing pixel data and a phase information number, an input register 11 transferring input pixel data to a local memory 15, an input skip register 12 and an output skip register 14 storing pixel skip information, an operation processing section 16 performing a prescribed filter operation based on a phase information number, and an output register 13 storing input pixel data taken out from the memory 15 or pixel data after operation, the processors 10 store discretely input pixel data in the input register 11 based on pixel skip information at the time of enlarging the number of pixels, inversely, store discretely pixel data from the memory 15 in the output register 14 based on pixel skip information in reducing the number of pixels.
-
公开(公告)号：JPH0969061A
公开(公告)日：1997-03-11
申请号：JP24662795
申请日：1995-08-30
Applicant: SONY CORP
Inventor： IWASE SEIICHIRO , KUROKAWA MASUYOSHI , YAMAZAKI TAKAO , OKI MITSUHARU
Abstract: PROBLEM TO BE SOLVED: To improve the processing capability of a multiple parallel digital signal processor type video signal processor which has bit processing elements arrayed linearly. SOLUTION: This processor consists of at least a serial access memory part 21, a data memory part 22, and an ALU array part 23 and the data memory part 22 has memory constitution with >=2 ports; and then the need for data transfer between two data memory parts prior to processing operation that conventional two-data-memory constitution has is eliminated, and consequently the video signal processor 20 which is greatly improved in processing capability is obtained.
-
公开(公告)号：JPH0467227A
公开(公告)日：1992-03-03
申请号：JP17927490
申请日：1990-07-06
Applicant: SONY CORP
Inventor： KUROKAWA MASUYOSHI
Abstract: PURPOSE:To minimize the number of times of the addition/subtraction and to increase the multiplying speed by making the numbers of '1s' and '-1s' same or decrease in a ternary expression. CONSTITUTION:A multiplication circuit which is suitably applied to an integrated high-speed parallel multiplier used for a digital filter, a digital signal processor, etc., is provided with an expression converter which converts a multiplier expressed in a complement of 2 into a ternary expression where the part of (n) pieces (n: an integer >=2) of continuous '1s' is expressed in (n - 1) pieces of '0s' and '-1s' and an addition/subtraction circuit which performs the shift addition of a multiplicand with '1' of the value of the digits of the ternary expression and then the shift subtraction of the multiplicand with '-1' of the digit value of the ternary expression. Thus it is possible to obtain the product of the multiplier and the multiplicand in the average least addition/subtraction frequency. In this respect, the multiplication circuit is provided with a register 3, a code inverter 5, accumulator 7, a register 8, an expression converter 9, a control circuit 10, a shifter 11, and a data selector 12.
-
公开(公告)号：JP2009077383A
公开(公告)日：2009-04-09
申请号：JP2008186099
申请日：2008-07-17
Inventor： IHARA TOSHINORI , OKADA SHINTARO , NISHI TOMOHIRO , NISHIBORI KAZUHIKO , KUROKAWA MASUYOSHI
IPC: H04N7/01
Abstract: PROBLEM TO BE SOLVED: To suppress the breakdown of a generated interpolated image even in an image having a large brightness change which may be easily broken down in motion compensation processing using a motion vector in generating an interpolated image. SOLUTION: A sum-of-absolute-differences calculation unit 12a calculates a sum of absolute differences between corresponding pixels in a notice block of a notice pixel in an input image and in a reference block of a reference pixel in a just preceding image. A comparison unit 12b compares the sums of absolute differences to find out a minimum sum of absolute differences. A motion vector calculation part 12c extracts a motion vector of the notice pixel on the basis of the reference pixel having the minimum sum of absolute differences and the notice image. A motion compensation processing unit 13 generates an MC image by adopting the pixel values of respective pixels in the input image as the pixel values of pixels in the MC image on the basis of the motion vector. An accumulation unit 14a cumulatively adds sums of absolute differences in the input image which correspond to respective pixels in the MC image. A synthesis unit 14c synthesizes respective pixels in the input image and respective pixels in the corresponding MC image on the basis of the cumulative addition result to generate an interpolated image. COPYRIGHT: (C)2009,JPO&INPIT
Abstract translation: 要解决的问题：即使在具有大的亮度变化的图像中也可以抑制所生成的内插图像的破坏，该图像在生成内插图像时使用运动矢量进行运动补偿处理时容易分解。 解决方案：绝对差值计算单元12a计算输入图像中的通知像素的通知块中的相应像素与刚刚在前一个中的参考像素的参考块中的绝对差之和 图片。 比较单元12b比较绝对差的和以找出绝对差的最小和。 运动矢量计算部分12c基于具有最小绝对差和和通知图像的参考像素提取通知像素的运动矢量。 运动补偿处理单元13基于运动矢量，通过采用输入图像中的各像素的像素值作为MC图像中的像素的像素值来生成MC图像。 累积单元14a累积地添加与MC图像中的各个像素对应的输入图像中的绝对差的和。 合成单元14c基于累积加法结果合成输入图像中的相应像素和相应MC图像中的各个像素，以生成内插图像。 版权所有（C）2009，JPO＆INPIT
-
Patent Agency Ranking
公开(公告)号：JP2009038619A
公开(公告)日：2009-02-19
申请号：JP2007201591
申请日：2007-08-02
Inventor： OKADA SHINTARO , NISHIBORI KAZUHIKO , NISHI TOMOHIRO , IHARA TOSHINORI , KUROKAWA MASUYOSHI
Abstract: PROBLEM TO BE SOLVED: To provide an image processing device and method, and program for more surely detecting a black belt. SOLUTION: The image processing device detects a region 11-1 being the black belt by detecting a boundary between black lines which are continuously arranged downward from the upper edge of an input image and a line which is not a black line, and detects a region 11-2 being the black belt by detecting a boundary between lines which are continuously arranged downward from the edge of a prescribed area of a lower side of the input image and are not black lines, and the black line. In addition, the image processing device detects regions 12-1 and 12-2 being the black belt by detecting the positions of boundaries between the regions 12-1 and 12-2 and the central effective image of the input image and performing majority processing of the positions about respective lines of the image obtained by eliminating the region 11-1 and the region 11-2 from the input image. COPYRIGHT: (C)2009,JPO&INPIT
Abstract translation: 要解决的问题：提供一种用于更可靠地检测黑带的图像处理装置和方法以及程序。 解决方案：图像处理装置通过检测从输入图像的上边缘向下连续的黑线与不是黑线的线连续布置的黑线之间的边界来检测作为黑带的区域11-1，以及 通过检测从输入图像的下侧的规定区域的边缘向下连续并且不是黑线的线条之间的边界以及黑线，来检测作为黑带的区域11-2。 此外，图像处理装置通过检测区域12-1和12-2之间的边界的位置和输入图像的中心有效图像来检测作为黑带的区域12-1和12-2，并且执行多数处理 通过从输入图像中消除区域11-1和区域11-2而获得的图像的各行的位置。 版权所有（C）2009，JPO＆INPIT
-
公开(公告)号：JP2005284486A
公开(公告)日：2005-10-13
申请号：JP2004094789
申请日：2004-03-29
Inventor： AOYAMA KOJI , NISHIBORI KAZUHIKO , XAVIER MICHEL , KUROKAWA MASUYOSHI
CPC classification number: G06T7/238 , G06T7/223 , G06T2207/10016
Abstract: PROBLEM TO BE SOLVED: To accurately obtain motion vectors in the unit of pixels. SOLUTION: When a noted block with the presence of noted pixels is a block C, and near-by blocks vertically or horizontally adjacent to the block C which is the noted block, are blocks A, B, D, E, the respective motion vectors a-e in the unit of blocks are made candidates of motion vectors in the unit of pixels for the noted pixels, and actually using the motion vectors a-e in the unit of blocks for the noted pixels, the motion vectors minimizing the difference of pixel values between the pixels used for interpolation between fields are made the motion vectors in the unit of pixels for the noted pixels. COPYRIGHT: (C)2006,JPO&NCIPI
Abstract translation: 要解决的问题：准确地获得以像素为单位的运动矢量。 解决方案：当具有指示像素的记录的块是块C时，并且与块C相邻的块垂直或水平附近是块A，B，D，E， 将以块为单位的各个运动矢量ae作为用于所述像素的像素单位的运动矢量的候选，并且实际使用以所述像素为单位的单位的运动矢量ae，使得像素差异最小的运动矢量 将用于场之间的插值的像素之间的值作为所述像素的像素单位中的运动矢量。 版权所有（C）2006，JPO＆NCIPI
-
公开(公告)号：JP2003189259A
公开(公告)日：2003-07-04
申请号：JP2001380765
申请日：2001-12-13
Applicant: SONY CORP
Inventor： HOSHINO TAKANARI , SARUGAKU TOSHIO , SOMEYA IKUO , KONDO MAKOTO , NISHIBORI KAZUHIKO , AOYAMA KOJI , MOGI YUKIHIKO , UEKI NOBUO , KUROKAWA MASUYOSHI
Abstract: PROBLEM TO BE SOLVED: To smoothen motion of an image of an image signal generated by subjecting a telecine-converted image to double speed conversion while suppressing plane flicker disturbance even in various image variations. SOLUTION: The image signal which is generated by subjecting the telecine- converted image to double speed conversion and, the one film frame of which is formed from four fields is inputted. Each field is identified on the basis of a difference value between operated pixel signal levels. The position of a detected pixel is shifted so as to sequentially come close to the position of a pixel shifted in the fourth field, in the identified first field in a direction opposite from a motion vector, in the identified fourth field in the direction of the motion vector, and further in the identified second and third fields in accordance with following made from the first field to the subsequent fields. COPYRIGHT: (C)2003,JPO
-
公开(公告)号：JP2003189257A
公开(公告)日：2003-07-04
申请号：JP2001380761
申请日：2001-12-13
Applicant: SONY CORP
Inventor： HOSHINO TAKANARI , SARUGAKU TOSHIO , SOMEYA IKUO , KONDO MAKOTO , UEKI NOBUO , KUROKAWA MASUYOSHI , NISHIBORI KAZUHIKO , AOYAMA KOJI , MOGI YUKIHIKO
Abstract: PROBLEM TO BE SOLVED: To smoothen motion of an image of an image signal generated by subjecting a telecine-converted image to double speed conversion while suppressing plane flicker disturbance. SOLUTION: The image signal which is generated by subjecting the telecine- converted image to double speed conversion and, the one film frame of which is formed from four fields is inputted. A first field is identified on the basis of a difference value between operated pixel signal levels, and the position of a detected pixel is shifted in the vector direction of a motion vector such that an amount of shift is progressively increased in accordance with a transition made from the identified first field to the subsequent fields. COPYRIGHT: (C)2003,JPO
-
公开(公告)号：JPH1115801A
公开(公告)日：1999-01-22
申请号：JP16707697
申请日：1997-06-24
Applicant: SONY CORP
Inventor： KUROKAWA MASUYOSHI
Abstract: PROBLEM TO BE SOLVED: To easily execute the processing of a data arithmetic unit. SOLUTION: A selector 60A is arranged in a 1st processor element(PE) out of N PEs 15 and a selector 60B is arranged in an N-th PE 15. The data of a data memory 12 in the 1st PE 15 and values '0' and '1' are supplied to the selector 60A and the data of a data memory 12 in the N-th PE 15 and the values '0', '1' are supplied to the selector 60B, so that a program control circuit 17 can select and output the data of the selectors 60A, 60B.
-
-
-
-
-
-
-
-
-
Search Results
65
records
(took 0.032 seconds)
