公开(公告)号：JPH02272748A

公开(公告)日：1990-11-07

申请号：JP9300289

申请日：1989-04-14

Applicant: SONY CORP

Inventor： SATO JUNICHI ,  NISHIYAMA KAZUO ,  KIYOTA HISAHARU ,  MORITA YASUSHI

IPC: H01L21/3205 ,  H01L21/31 ,  H01L21/768

Abstract: PURPOSE:To improve stability of a process and reliability of a device by forming an insulating film selectively in a peripheral part or an edge surface of a semiconductor wafer and by filling up only a contact hole in the semiconductor wafer with tungsten. CONSTITUTION:A pad SiO2 film 7 and a silicon nitride film 8 are formed on a surface of a semiconductor wafer 1 whereon an integrated circuit element is formed. Then, a region whereto photoresist is not applied is provided from an outer periphery of the wafer 1 to a specified region. After the films 8, 7 are etched, resist is removed. Selective oxidation is carried out including a peripheral part 5 and an edge surface 6 using the film 8 as a mask. After an insulating film 9 is formed, the films 8, 7 are removed. Furthermore, an insulating film 2 is provided to a surface of the wafer 1. After a contact hold 3 is made through photolithography, tungsten is made to grow only inside the hole using WF6, SiH4 gas. Thereby, unnecessary tungsten is prevented from growing and reliability of process and device can be improved.

公开(公告)号：JPH02148834A

公开(公告)日：1990-06-07

申请号：JP30327088

申请日：1988-11-30

Applicant: SONY CORP

Inventor： MORITA YASUSHI ,  MUROYAMA MASAKAZU

IPC: H01L21/205

Abstract: PURPOSE:To suppress automatic doping at the downstream side of gas flow and to improve the yield of a device by providing means for absorbing impurity generated from the epitaxially grown part of a wafer at a lower temperature than that of the grown part of the wafer at gas discharging means side of the wafer. CONSTITUTION:A wafer placing base 13 for placing a wafer 12 and a gas supply nozzle 14 are disposed in a reaction vessel 11. A high frequency induction heating coil 15 is disposed under the base 13. A groove 13a is formed at the position on the upper face of the base 13 at the side of gas discharging means, and the wafer 12 on the groove 13a is not conducted with heat from the base 13. Accordingly, the part of the gas discharge side shown by a broken line of the wafer 12 is a low temperature part 12a, and the other part becomes a high temperature part 12b. The temperature difference between the parts 12a and 12b is desirably approx. 30-100 deg.C. With such a structure, the impurity evaporated from the wafer 12 is effectively collected to the part 12a, and the automatic doping of the part 12b can be suppressed.

公开(公告)号：JPH01319943A

公开(公告)日：1989-12-26

申请号：JP15285488

申请日：1988-06-21

Applicant: SONY CORP

Inventor： NISHIYAMA KAZUO ,  MORITA YASUSHI

IPC: H01L21/316 ,  H01L21/336 ,  H01L29/78

Abstract: PURPOSE:To prevent fining from being checked by re-diffusion, by applying a beam of 20nm or shorter wavelength to the whole surface of a main body after an insulating layer is formed and selectively forming an oxide thin film on the surface of the main body excluding the part where element separation areas are formed. CONSTITUTION:Element separation areas 3 comprising insulating layers having channel stop areas 2 thereunder are formed on a main body 1, and an energy beam of a 200nm or shorter wavelength is applied at once or gradually on the whole surface of the main body 1 to selectively form a semiconductor oxide thin film 4 on the surface, excluding the part where the element separation areas 3 are formed, of the main body 1. The energy beam of 200nm or shorter wavelength is absorbed well to the main body 1 and the element separation areas 3, and enters them to the depth of about at most 100Angstrom to heat only the surface thereof. Therefore, the channel stop areas 2 formed under the areas 3 are hardly heated.

公开(公告)号：JPH01216520A

公开(公告)日：1989-08-30

申请号：JP4318588

申请日：1988-02-25

Applicant: SONY CORP

Inventor： MORITA YASUSHI

IPC: H01L21/20 ,  H01L21/268

Abstract: PURPOSE:To decrease the escape of heat from a heated semiconductor layer and to perform annealing with low energy, by supporting a sample that is formed with the semiconductor layer in a space over a light transmitting insulating substrate, and projecting light from the side of the light transmitting insulating substrate. CONSTITUTION:A polycrystalline silicon layer is formed by a low pressure CVD method on one surface of a quartz substrate 1. Silicon ions that are neutral ions are implanted into the polycrystalline silicon layer. A non-single crystal semiconductor layer 2 as an amorphous- state silicon layer is formed. A recess part 7 having the size approximately corresponding to the area of a sample 3 is provided in a holder 6. Step parts 8 are provided at the sample holder 6 so as to hold the edge parts of the sample on the upper peripheral parts of the recess part 7. The sample 3 is arranged and supported on the step parts 8 of the upper parts of the recess part 7 in the sample holder 6. The sample 3 is supported in a space so that the non-single crystal semiconductor layer 2 faces downward 2. Under this state, laser light, i.e., excimer laser, is projected on the sample 3 from the side of the quartz substrate 1. Annealing for growing the diameter of the crystal grain is performed for the non-single crystal semiconductor layer 2. Since the laser is projected on the sample 3 from the side of the quartz substrate 1 in this way and annealing is performed, the diameter of the crystal grain can be made large with low energy.

公开(公告)号：JPH0196923A

公开(公告)日：1989-04-14

申请号：JP25526687

申请日：1987-10-09

Applicant: SONY CORP

Inventor： NODA SANEYA ,  MORITA YASUSHI

IPC: H01L21/205

Abstract: PURPOSE:To make impurities in a semiconductor substrate decrease auto doping into an epitaxial layer, by performing baking at a temp. 1100 deg.C or more at reduced pressure and epitaxial growth at the temp. 900 deg.C or less at reduced pressure as well. CONSTITUTION:An n type buried layer 2 having the concentration of impurities, for example, 2X10 cm is formed at a p-type Si substrate 1, by doping, for example, arsenic with processes of ion-implantation or diffusion. Then, the Si substrate 1 is put in, for example, a barrel furnace-type epitaxial growth device and the Si substrate 1 is baked with H2 at a temp. 1100 deg.C or more for 5 min. at such a condition of, for example 1100 deg.C and 23Torr. Even though arsenic evaporates from the buried layer in this way, no arsenic is attracted very much to the surface of the Si substrate 1 because of the fact that it is at high temp. and reduced pressure. Further, this device allows an n-type Si epitaxial layer having the concentration of the impurities, for example, 2X10 cm to perform epitaxial growth. The epitaxial growth is carried out at a temp. 900 deg.C or less at such a condition of, for example, 900 deg.C and 32-34Torr by using silanedichlorosilane and the like as a reaction gas. In this way no arsenic is attracted to the surface of the Si substrate 1.

公开(公告)号：JPS6388821A

公开(公告)日：1988-04-19

申请号：JP23333286

申请日：1986-10-02

Applicant: SONY CORP

Inventor： NODA JITSUYA ,  SATO JUNICHI ,  MORITA YASUSHI

IPC: H01L21/205

Abstract: PURPOSE:To improve the controllability of the film thickness of a single crystal semiconductor, and to realize flattening easily by forming a nonsingular crystal layer so as to expose the sidewall of a groove section in a single crystal semiconductor substrate and vapor-growing the single crystal semiconductor, using the sidewall of the groove section as species. CONSTITUTION:An silicon oxide film 2 is shaped onto a single crystal silicon substrate 1, and one part of the oxide film 2 is removed through etching to form a groove section 3. The silicon oxide film 2 is gotten rid of, an silicon nitride film 4 is shaped, and only a groove-section sidewall 3a is left through etching having high selectivity. A main-surface oxide film 5 and a bottom oxide film 6 are formed, using the sidewall 3a as a mask, and the silicon nitride film 4 is taken off through etching to expose only the groove-section sidewall 3a. SiH4 gas, SiHxCl4-x, etc., are employed as a source gas, and Hcl gas, H2 gas, etc., having etching properties are used and a single crystal semiconductor layer 7 is shaped in the groove section 3. Vapor growth is progressed, and the layer 7 is made thicker than final thickness. The main-surface oxide film 5 has an etching rate different from the single crystal semiconductor layer 7, thus easily flattening the whole surface through etchback.

公开(公告)号：JPS61136674A

公开(公告)日：1986-06-24

申请号：JP25635484

申请日：1984-12-04

Applicant: Sony Corp

Inventor： NODA SANENARI ,  HAYASHI HISAO ,  MORITA YASUSHI

IPC: C30B25/12 ,  C23C16/00 ,  C23C16/44 ,  C23C16/458 ,  H01L21/02

Abstract: PURPOSE: To prevent the contamination of a semiconductor wafer by taking in and out by placing an auxiliary susceptor which can be taken out on a susceptor fixed in a reactor and by bringing the wafer into a vapor phase reaction on the auxiliary susceptor.
CONSTITUTION: A susceptor 4 is fixed in a vapor phase reactor, an auxiliary susceptor 21 which can be taken out is placed on the susceptor 4, and a semiconductor wafer 2 is mounted on the susceptor 21 and brought into a vapor phase reaction. The auxiliary susceptor 21 is made of Si and has a central recess 22 for stably mounting the wafer 2. The bottom of the recess 22 is shaped so that slip lines are hardly produced. After the wafer 2 is mounted in the recess 22, three peripheral parts A, B, C of the auxiliary susceptor 21 are attracted by a quartz vacuum chuck or the like, and the auxiliary susceptor 21 is placed on the susceptor 4. In a similar way, the auxiliary susceptor 21 is taken out of the reactor.
COPYRIGHT: (C)1986,JPO&Japio

Abstract translation: 目的：通过放置可以取出固定在反应器中的基座上的辅助基座，并通过使辅助基座上的气相反应来防止半导体晶片的污染。 构成：将基座4固定在气相反应器中，将可取出的辅助基座21放置在基座4上，将半导体晶片2安装在基座21上并进行气相反应。 辅助感受体21由Si制成，并具有用于稳定地安装晶片2的中心凹部22.凹部22的底部成形为几乎不产生滑动线。 在晶片2安装在凹部22中之后，辅助基座21的三个周边部分A，B，C被石英真空卡盘等吸引，辅助基座21被放置在基座4上。 方式，将辅助基座21从反应器中取出。

公开(公告)号：JPS61132594A

公开(公告)日：1986-06-20

申请号：JP25127484

申请日：1984-11-28

Applicant: Sony Corp

Inventor： HAYASHI HISAO ,  NODA SANENARI ,  MORITA YASUSHI

IPC: C30B25/10 ,  H01L21/205

Abstract: PURPOSE: To remove the clouding of a bell-jar caused by the deposit by etching with HCl, and to enable the epitaxial treatment under the clear inspection of the inside of the bell-jar, in a gas-phase reactor having double bell-jar structure, by heating the inner bell-jar with a laser beam, etc., at the part just below the inspection window.
CONSTITUTION: A gas-phase reactor having a double bell-jar structure and suitable for epitaxial growth of silicon is supplied with hot HCl prior to the start of the gas- phase reaction to etch and remove the polycrystalline silicon. A laser beam emitted from the light source 20 is radiated through the inspection window 8 to the inner bell-jar 2 at a part just below the window 8. The clouding of the window caused by a small amount of polycrystal-line silicon evaporated at high temperature and deposited to the window is etched and removed with HCl by this process. The radiation of laser is stopped, and the substrate to be subjected to the epitaxial growth, e.g. a silicon substrate, is placed on the supporting table 3. The raw material gas such as SiH
4 and the carrier gas such as H
2 are introduced into the bell-jar through the nozzle 7 of the reaction gas feed pipe 6, the cooling H4d2 gas is supplied to the space between the bell-jars 1 and 2 through the line 11, and the substrate is heated with a heating means to effect the epitaxial growth treatment.
COPYRIGHT: (C)1986,JPO&Japio

Abstract translation: 目的：通过用HCl蚀刻来除去由沉积物引起的钟罩的浑浊，并且在具有双钟罩的气相反应器中，在清洁检查钟罩的内部能够进行外延处理 通过在检查窗口正下方的部分用激光束等加热内部钟罩，结构。 构成：在气相反应开始之前，将具有双钟罩结构并适于硅外延生长的气相反应器供入热HCl以蚀刻和除去多晶硅。 从光源20发射的激光束在窗口8正下方的一部分通过检查窗8被辐射到内部钟形瓶2.由少量多晶硅硅蒸发的窗口的浊度高 通过该方法用HCl蚀刻并除去温度并沉积到窗口的温度。 停止激光的辐射，并且要进行外延生长的衬底，例如， 将硅衬底放置在支撑台3上。诸如SiH 4的原料气体和诸如H 2的载气通过反应气体供给管6的喷嘴7引入钟罩中，冷却H4d2气体为 通过管线11供应到钟形瓶1和2之间的空间，并且用加热装置加热衬底以进行外延生长处理。

公开(公告)号：JPS61117280A

公开(公告)日：1986-06-04

申请号：JP23925884

申请日：1984-11-13

Applicant: Sony Corp

Inventor： MORITA YASUSHI ,  NODA JITSUYA ,  HAYASHI HISAO

IPC: C23C16/44 ,  C23C16/54

CPC classification number: C23C16/54

Abstract: PURPOSE:To cool effectively the inside reaction chamber of a gaseous phase reactor made into double construction and to permit the increase in the size of said reactor by supplying a cooled gas into the space between the inside reaction chamber and outside reaction chamber. CONSTITUTION:The reaction chamber made into the double construction is constituted of a stainless steel bell-jar 2 on the outside and a quartz inner bell- jar 4 on the inside and a reactive gas is supplied with gaseous hydrogen as a carrier gas through a piping 12 and is ejected from a nozzle 8 through a supply port 11 into the vessel to cause gaseous phase reaction. The gaseous hydrogen is supplied via a peep window 15 to the space between the bell-jar 2 and the bell-jar 4 through a piping 14 and a supply port 13. The gaseous hydrogen is cooled by passing liquid nitrogen into a coiled piping 17. The bell-jar 4 is thus effectively cooled and the product having high quality is produced.

Abstract translation: 目的：为了有效地冷却制成双重结构的气相反应室的内部反应室，并通过将冷却的气体供入内部反应室和外部反应室之间的空间来允许所述反应器的尺寸增加。 构成：制成双重结构的反应室由外部的不锈钢钟形瓶2和内部的石英钟罩4构成，反应气体通过配管供给作为载气的气态氢气 并且从喷嘴8通过供应口11喷射到容器中以引起气相反应。 气态氢气通过窥视窗15通过管道14和供应口13供应到钟形瓶2和钟形瓶4之间的空间。气态氢气通过将液氮通入螺旋管道17来冷却。 因此，钟形瓶4被有效地冷却并产生具有高品质的产品。

公开(公告)号：JP2003179064A

公开(公告)日：2003-06-27

申请号：JP2001375562

申请日：2001-12-10

Applicant: SONY CORP

Inventor： MORITA YASUSHI

IPC: H01L21/28 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3213

Abstract: PROBLEM TO BE SOLVED: To easily and surely form, with the existing photolithography technology, a wiring pattern in the line width which is thinner than that of a resist pattern formed by the photolithography. SOLUTION: A mask layer 6 consisting of SiOC is provided on a gate electrode layer 3 and a photoresist layer 4 is also provided on this mask layer 6. A resist mask 4a is formed to this photoresist layer 4 with the ordinary photolithography technology and the mask layer 6 is dry-etched using this resist mask 4a. Thereafter, the resist mask 4a is removed and the surface of the remaining mask layer 6 is denatured to the SiOX layer 6a through the ashing in the oxygen plasma. The formed SiOX layer 6a is removed with hydrofluoric acid to form the SiOC mask 6b, the gate electrode layer 3 is etched using this SiOC mask 6b, and thereby a wiring pattern 3a of the gate electrode can be obtained. COPYRIGHT: (C)2003,JPO