公开(公告)号：JPS6045077A

公开(公告)日：1985-03-11

申请号：JP15292583

申请日：1983-08-22

Applicant: SONY CORP

Inventor： HAYASHI HISAO ,  YAMOTO HISAYOSHI ,  NODA JITSUYA

IPC: H01L31/10 ,  H01L31/105

Abstract: PURPOSE:To obtain the titled device excellent in the characteristic of high frequency and that of photosensitivity frequency and easy in design by a method wherein a semiconductor layer containing a low concentration inpurity is provided on a semiconductor containing the first conductivity type impurity of high concentration, and further a semiconductor layer conaining a lower concentration is provided thereon. CONSTITUTION:After n layers 2 and 3 are formed in both sides of an n type Si substrate 1 by thermal diffusion of an n type impurity to a high concentration, then n layer 2 is removed by polishing, and then an n type Si layer 13 is epitaxially grown on one main surface 1a of the exposed substrate 1. Next, an SiO2 film is formed by thermal oxidation of the surface, thereafter an aperture 4a is formed by etch-removal of a fixed section, and a p layer 5 is formed by thermal diffusion of a p type impurity to a high concentration. Afterwards, the SiO2 film is etch-removed and a non-reflection film 6 is adhesion-formed, then a fixed section is etch-removed, and an electrode 7 is adhesion-formed in an aperture 6a. Besides, an electrode 10 of double-layer structure is formed on the other surface of the substrate 1. Finally, a P-I-N diode is obtained by cutting along a cutting line 11.

公开(公告)号：JPS59188140A

公开(公告)日：1984-10-25

申请号：JP6270183

申请日：1983-04-08

Applicant: Sony Corp

Inventor： OOUCHI NORIKAZU ,  NODA JITSUYA

IPC: H01L27/04 ,  H01L21/20 ,  H01L21/28 ,  H01L21/331 ,  H01L21/76 ,  H01L21/761 ,  H01L21/822 ,  H01L29/43 ,  H01L29/73

CPC classification number: H01L21/761

Abstract: PURPOSE:To obtain an IC device having high integration and high performance by forming an insulating layer having a hole on one main surface of a semiconductor substrate, forming a semiconcuctor layer on the insulating layer and the hole by a vapor phase growth, and removing the semiconductor layer to the prescribed thickness, thereby forming an element on the semiconductor layer of the hole. CONSTITUTION:After an N type collector buried layer 11 is formed on one main surface of a P type Si semiconductor substrate 1, an insulating layer 2 such as an SiO2 is formed. Then, holes 12, 13 to become an intrinsic portion and a collector electrode leading region are respectively formed by a normal etching process at the prescribed portion of the layer 2. Then, epitaxial growth is performed on the entire substrate 1, N type epitaxial layers 4, 4' are formed in the holes 12, 13, and an N type polycrystalline Si layer 5 is formed on the layer 2. An SiH4 is optimally used in the epitaxial growth. Then, vapor phase etching using HCl is performed, thereby forming so that the layers 4, 4' and the layer 5 become flush with each other.

Abstract translation: 目的：为了通过在半导体衬底的一个主表面上形成具有孔的绝缘层来获得具有高集成度和高​​性能的IC器件，通过气相生长在绝缘层和孔上形成半导体层，并且除去 半导体层到规定厚度，从而在孔的半导体层上形成元素。 构成：在P型Si半导体衬底1的一个主表面上形成N +型集电极埋层11之后，形成诸如SiO 2的绝缘层2。 然后，通过在层2的规定部分的常规蚀刻工艺分别形成成为本征部分的孔12,13和集电极引线区域。然后，在整个衬底1上进行外延生长，N型外延层 4,4'形成在孔12,13中，并且在层2上形成N型多晶硅层5.在外延生长中SiH 4被最佳地使用。 然后，进行使用HCl的气相蚀刻，从而形成层4,4'和层5彼此齐平。

公开(公告)号：JPH027517A

公开(公告)日：1990-01-11

申请号：JP15848688

申请日：1988-06-27

Applicant: SONY CORP

Inventor： SUMI HIROBUMI ,  NODA JITSUYA

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L23/52

Abstract: PURPOSE:To avoid swallowing of a dopant and piercing-through of a metal layer and avoid the breakdown of a junction and achieve the reduction of a resistance by a method wherein a semiconductor layer and the metal layer are formed on an exposed contact region and both the layers are made to react with each other to form a metal silicide layer. CONSTITUTION:An oxide film 11 formed on a semiconductor region 1 is removed to expose a contact region 12. An Si or polycrystalline Si epitaxial layer is built up on the contact region 12 to form a semiconductor layer 2. A metal layer 3 is formed and, further, a metal silicide layer 4 is formed by silicidizing annealing. After that, an electrode is formed on the metal silicide layer 4. As the formed semiconductor layer 2 serves as a supply source of semiconductor material for forming silicide, swallowing of a dopant in a diffused layer caused by the erosion of the semiconductor region 1 and the erosion of silicon or the like in the diffused layer can be suppressed. With this constitution, the breakdown of a junction can be avoided and, further, the reduction of the resistance of the diffused layer can be realized.

公开(公告)号：JPS6388821A

公开(公告)日：1988-04-19

申请号：JP23333286

申请日：1986-10-02

Applicant: SONY CORP

Inventor： NODA JITSUYA ,  SATO JUNICHI ,  MORITA YASUSHI

IPC: H01L21/205

Abstract: PURPOSE:To improve the controllability of the film thickness of a single crystal semiconductor, and to realize flattening easily by forming a nonsingular crystal layer so as to expose the sidewall of a groove section in a single crystal semiconductor substrate and vapor-growing the single crystal semiconductor, using the sidewall of the groove section as species. CONSTITUTION:An silicon oxide film 2 is shaped onto a single crystal silicon substrate 1, and one part of the oxide film 2 is removed through etching to form a groove section 3. The silicon oxide film 2 is gotten rid of, an silicon nitride film 4 is shaped, and only a groove-section sidewall 3a is left through etching having high selectivity. A main-surface oxide film 5 and a bottom oxide film 6 are formed, using the sidewall 3a as a mask, and the silicon nitride film 4 is taken off through etching to expose only the groove-section sidewall 3a. SiH4 gas, SiHxCl4-x, etc., are employed as a source gas, and Hcl gas, H2 gas, etc., having etching properties are used and a single crystal semiconductor layer 7 is shaped in the groove section 3. Vapor growth is progressed, and the layer 7 is made thicker than final thickness. The main-surface oxide film 5 has an etching rate different from the single crystal semiconductor layer 7, thus easily flattening the whole surface through etchback.

公开(公告)号：JPS61117280A

公开(公告)日：1986-06-04

申请号：JP23925884

申请日：1984-11-13

Applicant: Sony Corp

Inventor： MORITA YASUSHI ,  NODA JITSUYA ,  HAYASHI HISAO

IPC: C23C16/44 ,  C23C16/54

CPC classification number: C23C16/54

Abstract: PURPOSE:To cool effectively the inside reaction chamber of a gaseous phase reactor made into double construction and to permit the increase in the size of said reactor by supplying a cooled gas into the space between the inside reaction chamber and outside reaction chamber. CONSTITUTION:The reaction chamber made into the double construction is constituted of a stainless steel bell-jar 2 on the outside and a quartz inner bell- jar 4 on the inside and a reactive gas is supplied with gaseous hydrogen as a carrier gas through a piping 12 and is ejected from a nozzle 8 through a supply port 11 into the vessel to cause gaseous phase reaction. The gaseous hydrogen is supplied via a peep window 15 to the space between the bell-jar 2 and the bell-jar 4 through a piping 14 and a supply port 13. The gaseous hydrogen is cooled by passing liquid nitrogen into a coiled piping 17. The bell-jar 4 is thus effectively cooled and the product having high quality is produced.

Abstract translation: 目的：为了有效地冷却制成双重结构的气相反应室的内部反应室，并通过将冷却的气体供入内部反应室和外部反应室之间的空间来允许所述反应器的尺寸增加。 构成：制成双重结构的反应室由外部的不锈钢钟形瓶2和内部的石英钟罩4构成，反应气体通过配管供给作为载气的气态氢气 并且从喷嘴8通过供应口11喷射到容器中以引起气相反应。 气态氢气通过窥视窗15通过管道14和供应口13供应到钟形瓶2和钟形瓶4之间的空间。气态氢气通过将液氮通入螺旋管道17来冷却。 因此，钟形瓶4被有效地冷却并产生具有高品质的产品。

公开(公告)号：JPS63100748A

公开(公告)日：1988-05-02

申请号：JP24553686

申请日：1986-10-17

Applicant: SONY CORP

Inventor： NODA JITSUYA ,  MORITA YASUSHI

IPC: H01L21/3205

Abstract: PURPOSE:To enhance safety by a method wherein, in an opening part wherein a semiconductor layer is formed and an electrical connection is obtained, a silicate glass layer containing an impurity is laminated on an insulating layer forming the opening part and the impurity is introduced in the semiconductor layer from this silicate glass layer at the time of formation of the semiconductor layer. CONSTITUTION:An SiO2 layer 2 and an impurity-containing PSG glass layer 3 are laminated and adhered on an Si substrate 1 with an element region being formed thereon, a reactive ion etching is performed and an opening part 4 is bored correspondingly to the element region. Then, a semiconductor layer 5, which comes into contact to the element region, is buried in the opening part 4, yet at this time, the semiconductor layer 5 is constituted of poly Si made to contain an impurity using SiH2Cl2-HCl-PH3-H2 gas, for example. As a heat treatment is sure to be associated with to this, the P being contained in the glass layer 3 is also injected simultaneously in the layer 5 and to make lower the impurity concentration in the gas used before is made possible. Accordingly, the riskiness due to work is reduced.

公开(公告)号：JPS59188174A

公开(公告)日：1984-10-25

申请号：JP6270083

申请日：1983-04-08

Applicant: Sony Corp

Inventor： HAYASHI HISAO ,  NODA JITSUYA

IPC: H01L29/78

CPC classification number: H01L29/78

Abstract: PURPOSE:To enhance the integrating density of a semiconductor device by forming windows for leading electrodes of source and drain regions in a self-alignment. CONSTITUTION:An SiO2 layer 2, a polycrystalline silicon layer 3 and an Si3N4 layer 4 are formed on a P type silicon semiconductor substrate 1, and with the Si3N4 as a mask a field oxidized layer 5 is formed. A gate window is selectively opened, and a P type epitaxial layer 7 is grown. A gate oxidized layer 8 and a gate polycrystalline silicon 9 are formed. An N type impurity ions are implanted to the layer 3 to form N type source and drain regions 10, 11. A thermally oxidized film 12 is grown, the layer 4 is etched and removed, and source and drain electrodes 13, 14 of aluminum are formed. The layer 4 is used as mask in case of three times selective oxidations, and etched and removed eventually. Accordingly, the windows for leading the electrodes can be formed in a self-alignment.

Abstract translation: 目的：通过在自对准中形成源区和漏区的引导电极的窗口来提高半导体器件的积分密度。 构成：在P型硅半导体基板1上形成SiO 2层2，多晶硅层3和Si 3 N 4层4，以Si 3 N 4为掩模形成场氧化层5。 选择性地打开栅极窗口，并且生长P型外延层7。 形成栅极氧化层8和栅极多晶硅9。 将N型杂质离子注入到层3中以形成N型源极和漏极区域10,11。生长热氧化膜12，蚀刻和去除层4，并且铝的源极和漏极电极13,14 形成。 在选择性氧化三次的情况下，层4用作掩模，并最终蚀刻和去除。 因此，用于引导电极的窗口可以形成为自对准。

公开(公告)号：JPS59172247A

公开(公告)日：1984-09-28

申请号：JP4644883

申请日：1983-03-18

Applicant: Sony Corp

Inventor： HAYASHI HISAO ,  NODA JITSUYA ,  OOSHIMA TAKEFUMI

IPC: H01L21/76 ,  H01L21/20 ,  H01L21/762

CPC classification number: H01L21/76294

Abstract: PURPOSE:To isolate the surface so as to be flatten, and to miniaturize a device by forming an insulating layer with an opening section onto a main surface, shaping semiconductor layers to the upper section of the insulating layer and the opening section so that each upper surface is brought to approximately the same height through vapor phase growth and forming an element to the semiconductor layer of the opening section. CONSTITUTION:A semiconductor base body, a main surface thereof has a 100 face, such as a silicon semiconductor base body 11 is prepared, and an insulating layer in predetermined thickness such as an SiO2 layer 12 is applied and formed onto the base body. The necessary section of the SiO2 layer 12 is removed through selective etching, etc. to shape an opening section 13. An epitaxial layer 14 and a polycrystalline silicon layer 15 are each formed so that several upper surface is brought to approximately the same height. The vapor phase grown layer is etched only by the thickness of the polycrystalline silicon layer 15 extending over the whole surface. A necessary element is formed to the epitaxial layer 14 in the opening section 13. Since the element is formed to the epitaxial layer 14, the minute element is constituted, and the minute element region is isolated by the SiO2 layer 13.

Abstract translation: 目的：通过在主表面上形成具有开口部分的绝缘层来使表面隔离以使其平坦化并使器件小型化，将半导体层成形为绝缘层的上部和开口部分，使得每个上部 表面通过气相生长被带到大致相同的高度，并且形成元件到开口部分的半导体层。 构成：半导体基体，其主表面具有100个面，例如硅半导体基体11，并且将诸如SiO 2层12的预定厚度的绝缘层施加并形成在基体上。 通过选择性蚀刻等去除SiO 2层12的必要部分，以形成开口部分13.每个形成外延层14和多晶硅层15，使得几个上表面达到大致相同的高度。 仅通过在整个表面上延伸的多晶硅层15的厚度来蚀刻气相生长层。 在开口部分13中对外延层14形成必要的元件。由于元件与外延层14形成，所以构成微小元件，并且微小元素区域被SiO 2层13隔离。

公开(公告)号：JPS5931506A

公开(公告)日：1984-02-20

申请号：JP14184582

申请日：1982-08-16

Applicant: Sony Corp

Inventor： YAMOTO HISAYOSHI ,  NODA JITSUYA ,  YAMANAKA HIDEO

IPC: H01B5/14

公开(公告)号：JPH01216539A

公开(公告)日：1989-08-30

申请号：JP4323488

申请日：1988-02-25

Applicant: SONY CORP

Inventor： MORITA YASUSHI ,  NODA JITSUYA

IPC: H01L21/302 ,  H01L21/205 ,  H01L21/3065

Abstract: PURPOSE:To treat at a low temperature by removing an oxide film formed on a semiconductor layer, and employing one of phosphorus, boron and chlorine as gas for removing the oxide film and gas containing fluorine when a conductive layer is formed. CONSTITUTION:An oxide film formed on a semiconductor layer is removed, and, when a conductive layer such as an epitaxial layer or the like is formed over the removed part, gas containing phosphorus and fluorine and gas containing boron and fluorine or chlorine and fluorine are employed as gas for removing the oxide film. An intermediate species such as F* (radical) or HF, etc., is generated by the gas containing the fluorine and one of the phosphorus, boron and chlorine in a furnace. Thus, it is reacted with the oxide film such as SiO2+4F* SiF4+O2, and a natural oxide film on the semiconductor layer is removed. Such a reaction is generated at a relatively low temperature, and its process can be performed at the lower temperature.