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141 records (took 0.035 seconds)

    51.
    发明专利
    未知

    公开(公告)号：FR2833119A1

    公开(公告)日：2003-06-06

    申请号：FR0115529

    申请日：2001-11-30

    Applicant: ST MICROELECTRONICS SA

    Inventor： WUIDART LUC ,  BARDOUILLET MICHEL ,  PLAZA LAURENT

    IPC: G06F7/58 ,  G07F7/10 ,  G09C1/00 ,  G06K19/10 ,  H04L9/06 ,  G06K19/073 ,  H04L9/32

    Abstract: A digital identifier specific to integrated circuit chip is extracted from a physical parameter network (PPN) linked to integrated circuit chip manufacturing. The extracted identifier is submitted to several linear retroaction shift registers (20'), in order to output corresponding secret or encryption key. An Independent claim is also included for circuit for generating secret or encryption key.

    52.
    发明专利
    未知

    公开(公告)号：FR2829855A1

    公开(公告)日：2003-03-21

    申请号：FR0111920

    申请日：2001-09-14

    Applicant: ST MICROELECTRONICS SA

    Inventor： WUIDART LUC

    IPC: G06F21/32 ,  G06K19/10 ,  G06T7/00 ,  G07C9/00 ,  A61B5/117 ,  G06K9/60 ,  G07F7/12 ,  G06K9/46

    Abstract: A portable means of identification (10) has a fingerprint captor (1) which is associated with an extraction and digitization unit (12). An identifier (16) which is drawn from a system of physical parameters (17) such as a time constant relating to the captor is combined with the fingerprint data and scrambled (15). The result is compared (13) with a reference model (14) to give an identification An Independent claim is also included for: A portable identifying equipment which uses the captor physical parameter identifier

    54.
    发明专利
    未知

    公开(公告)号：FR2829265A1

    公开(公告)日：2003-03-07

    申请号：FR0111435

    申请日：2001-09-04

    Applicant: ST MICROELECTRONICS SA

    Inventor： WUIDART SYLVIE ,  WUIDART LUC ,  BARDOUILLET MICHEL ,  BALTHAZAR PIERRE

    IPC: G06F12/14 ,  G01K7/00 ,  G06F13/42 ,  G06F21/06 ,  G06K19/073 ,  H01L21/822 ,  H01L27/04

    Abstract: Method for detection of variations of an evironmental parameter (V,T) in an integrated circuit (1): (a) evaluate a propagation delay for retarding parts (21) sensitive to variations parameters environment, and; compare the delay current with respect to a reference value (REF). The measured delay current is compared to two predetermined minimum and maximum levels or a unique reference value defining a authorized operating range for the integrated circuit. The value from programmable retarder is determined as a function of the difference between the current value and reference value. The range of possible variation being predetermined.

    55.
    发明专利
    未知

    公开(公告)号：DE69718388D1

    公开(公告)日：2003-02-20

    申请号：DE69718388

    申请日：1997-07-24

    Applicant: ST MICROELECTRONICS SA

    Inventor： WUIDART LUC ,  BAILLY ALAIN

    IPC: H02M3/335 ,  H02M7/06

    Abstract: The supply unit is designed to supply a first high voltage and a second low voltage. The source for the first voltage includes a first capacitor(C1;C2) which receives a voltage from a rectifier. The first capacitor is connected in series with a DC low voltage source including in parallel: - a first diode(Da) in series with a second capacitor(Ca), - a rectifier(D) of opposite polarity to that of the first diode, and, - a voltage limiter(12) of the feedback type, the terminals(B,G) of the DC low voltage source correspond to the terminals of the second capacitor. The voltage limiter consists of a thyristor(Th) whose trigger and anode are connected by a Zener diode(Z). The unit also uses a current limiter(R) in series with the voltages sources.

    58.
    发明专利
    未知

    公开(公告)号：FR2823341A1

    公开(公告)日：2002-10-11

    申请号：FR0104585

    申请日：2001-04-04

    Applicant: ST MICROELECTRONICS SA

    Inventor： BARDOUILLET MICHEL ,  WUIDART LUC

    IPC: G01R31/28 ,  G11C5/00 ,  G11C8/20 ,  H01L21/822 ,  H01L27/04 ,  H03K5/15 ,  H03K5/19 ,  G06K19/073

    Abstract: The invention concerns an identification method and circuit (1) of the network type of parameters contained in an integrated circuit chip, comprising a single input terminal (2) for applying a signal (E) triggering an identification, the output terminals (31, 32, , 3i-1, 3i , , 3n-1, 3n) adapted to deliver a binary identifying code (B1, B2, Bi-1, Bi, , Bn-1, Bn), first electrical paths (P1, P2, , Pi, , Pn), individually connecting said input terminal to each output terminal, and means (4, 51, 52, , 5i, , 5n) for simultaneously integrating the binary states present in output of the electrical paths, each path inputting a delay sensitive to technological dispersions and/or of the integrated circuit fabrication method.

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