公开(公告)号：US20220393032A1

公开(公告)日：2022-12-08

申请号：US17888649

申请日：2022-08-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangwook KIM ,  Yunseong LEE ,  Sanghyun JO ,  Jinseong HEO

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/51 ,  H01L21/8234 ,  H01L21/28 ,  H01L29/66

Abstract: An integrated circuit includes transistors respectively including channel layers in a substrate, source electrodes and drain electrodes respectively contacting both sides of the channel layers, gate electrodes on the channel layers, and ferroelectrics layers between the channel layers and the gate electrodes. Electrical characteristics of the ferroelectrics layers of at least two of the transistors are different. Accordingly, threshold voltages of the transistors are different from each other.

公开(公告)号：US20220140104A1

公开(公告)日：2022-05-05

申请号：US17515969

申请日：2021-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinseong HEO ,  Yunseong LEE ,  Seunggeol NAM ,  Hagyoul BAE ,  Taehwan MOON ,  Sanghyun JO

IPC: H01L29/51 ,  H01L29/78

Abstract: Provided is a ferroelectric semiconductor device including a ferroelectric layer and two or more electrode layers. The semiconductor device may include a first electrode layer and a second electrode layer which have thermal expansion coefficients less than the thermal expansion coefficient of the ferroelectric layer. The difference between the thermal expansion coefficients of the second electrode layer and the ferroelectric layer may be greater than the difference between the thermal expansion coefficients of the first electrode layer and the ferroelectric. The second electrode layer may have a thickness greater than the thickness of the first electrode layer.

公开(公告)号：US20220005923A1

公开(公告)日：2022-01-06

申请号：US17171291

申请日：2021-02-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taehwan MOON ,  Jinseong HEO ,  Sangwook KIM ,  Yunseong LEE

IPC: H01L49/02 ,  H01L29/49 ,  H01L51/05 ,  H01L29/78 ,  H01L21/02 ,  H01L29/40 ,  H01L27/11507 ,  H01L27/1159

Abstract: Disclosed are a thin film structure and an electronic device including the same. The disclosed thin film structure includes a dielectric material layer between a first material layer and a second material layer. The dielectric material layer includes a dopant in a matrix material having a fluorite structure. The dielectric material layer is uniformly doped with a low concentration of the dopant, and has ferroelectricity.

公开(公告)号：US20200282484A1

公开(公告)日：2020-09-10

申请号：US16881377

申请日：2020-05-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinseong HEO ,  Yunseong LEE ,  Sanghyun JO

IPC: B23K3/08 ,  B23K3/06 ,  H01L23/00

Abstract: Provided are a logic switching device and a method of manufacturing the same. The logic switching device may include a domain switching layer adjacent to a gate electrode. The domain switching layer may include a ferroelectric material region and an anti-ferroelectric material region. The domain switching layer may be a non-memory element. The logic switching device may include a channel, a source and a drain both connected to the channel, the gate electrode arranged to face the channel, and the domain switching layer provided between the channel and the gate electrode.

公开(公告)号：US20200058658A1

公开(公告)日：2020-02-20

申请号：US16244243

申请日：2019-01-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinseong HEO ,  Yunseong LEE ,  Sanghyun JO

IPC: H01L27/1159 ,  H01L29/78 ,  G11C11/22 ,  H01L21/28 ,  H01L29/66

Abstract: Provided are an electronic device and a method of manufacturing the same. The electronic device may include a first device provided on a first region of a substrate; and a second device provided on a second region of the substrate, wherein the first device may include a first domain layer including a ferroelectric domain and a first gate electrode on the first domain layer, and the second device may include a second domain layer including a ferroelectric domain and a second gate electrode on the second domain layer. The first domain layer and the second domain layer may have different characteristics from each other at a polarization change according to an electric field. At the polarization change according to the electric field, the first domain layer may have substantially a non-hysteretic behavior characteristic and the second domain layer may have a hysteretic behavior characteristic.

公开(公告)号：US20170011930A1

公开(公告)日：2017-01-12

申请号：US15068110

申请日：2016-03-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seongjun JEONG ,  Seongjun PARK ,  Yunseong LEE

IPC: H01L21/308 ,  H01L29/06 ,  H01L21/3065 ,  H01L29/16

CPC classification number: H01L29/1606 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02527 ,  H01L21/02603 ,  H01L21/042 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/467 ,  H01L21/823412 ,  H01L27/088 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/66037 ,  H01L29/66045 ,  H01L29/775 ,  H01L29/778 ,  H01L29/78696 ,  H01L51/0045 ,  Y10S977/755 ,  Y10S977/888

Abstract: Methods of forming a graphene nanopattern, graphene-containing devices, and methods of manufacturing the graphene-containing devices are provided. A method of forming the graphene nanopattern may include forming a graphene layer on a substrate, forming a block copolymer layer on the graphene layer and a region of the substrate exposed on at least one side of the graphene layer, forming a mask pattern from the block copolymer layer by removing one of a plurality of first region and a plurality of second regions of the block copolymer, and patterning the graphene layer in a nanoscale by using the mask pattern as an etching mask. The block copolymer layer may be formed to directly contact the graphene layer. The block copolymer layer may be formed to directly contact a region of the substrate structure that is exposed on at least one side of the graphene layer.

Abstract translation: 提供形成石墨烯纳米图案的方法，含有石墨烯的装置以及制造含石墨烯的装置的方法。 形成石墨烯纳米图案的方法可以包括在基底上形成石墨烯层，在石墨烯层上形成嵌段共聚物层，在石墨烯层的至少一侧露出衬底的区域，从块形成掩模图案 通过除去嵌段共聚物的多个第一区域和多个第二区域中的一个，并且通过使用掩模图案作为蚀刻掩模，将纳米级的石墨烯层图案化。 嵌段共聚物层可以形成为直接接触石墨烯层。 嵌段共聚物层可以形成为直接接触在石墨烯层的至少一侧上暴露的衬底结构的区域。