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公开(公告)号：JP2008078916A
公开(公告)日：2008-04-03
申请号：JP2006254704
申请日：2006-09-20
Applicant: Toshiba Corp , 株式会社東芝
Inventor： MURAKAMI YASUSHI , TANAKA SHUICHI
Abstract: PROBLEM TO BE SOLVED: To provide an OFDM broadcast receiver and an OFDM broadcast relay device in which a circuit scale is effectively reduced, which has no delay and is applicable also to an SFN in a broadcast relay device which relays a broadcasting signal.
SOLUTION: In the OFDM broadcast receiver 100, eigenvalue decomposition is performed to receiving signals of respective receiving antennas 1-1 to 1-N by an eigenvalue decomposition part 4, an eigenvalue and an eigenvector corresponding to the eigenvalue are calculated, synthetic weight is generated by a synthetic weight generation part 5 from the eigenvector, the receiving signals are weighted and synthesized based on the synthetic weight by beam synthesizing parts 6-1 to 6-N and diversity-synthesizes an output from the beam synthesizing parts 6-1 to 6-N by a diversity synthesizing part 7. Thus, in the relay device equipped with the receiver 100, the circuit scale is reduced and a processing delay is eliminated in comparison with a conventional relay device.
COPYRIGHT: (C)2008,JPO&INPITAbstract translation: 要解决的问题：提供一种OFDM广播接收机和OFDM广播中继设备，其中电路规模被有效地减少，其没有延迟，并且也适用于广播中继设备中的SFN，其中继广播信号 。 解决方案：在OFDM广播接收机100中，通过特征值分解部分4执行特征值分解以接收各个接收天线1-1至1-N的信号，计算对应于特征值的特征值和特征向量，合成 权重由特征向量由合成权重生成部分5产生，接收信号根据合成权重由光束合成部分6-1至6-N进行加权和合成，并对来自光束合成部分6-1至6-N的输出进行分集合成， 1〜6-N。因此，与传统的中继装置相比，在配备有接收机100的中继装置中，电路规模减小，处理延迟消除。 版权所有（C）2008，JPO＆INPIT
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公开(公告)号：JPH05327646A
公开(公告)日：1993-12-10
申请号：JP12895392
申请日：1992-05-21
Applicant: TOSHIBA CORP
Inventor： FUJII YASUYUKI , TANAKA SHUICHI
Abstract: PURPOSE:To change the frame synchronization state into an asynchronization state by discriminating the presence of detection of a frame bit pattern in one frame so as to surely detect out of frame synchronism. CONSTITUTION:A decoder 10 takes into account information representing final frame bit location of a frame outputted from frame counters 4, 5 without fail and only when a last frame bit is detected at the final frame bit position, it is discriminated that a frame bit pattern of one frame is correctly detected. Even when a correct frame bit is not detected in a sub frame on its way as the case that out of frame synchronism takes place with sub frame synchronization taken for example, it is prevented that it is immediately discriminated in the frame synchronization state when a bit coincident with a last frame bit is detected at the final frame bit location and out of frame synchronism is surely checked.
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公开(公告)号：JPH05199270A
公开(公告)日：1993-08-06
申请号：JP1000792
申请日：1992-01-23
Applicant: TOSHIBA CORP , NIPPON TELEGRAPH & TELEPHONE
Inventor： TANAKA SHUICHI , FUJII YASUYUKI , HOSHINO HIROBUMI
Abstract: PURPOSE:To prevent the out of synchronism and to attain smooth changeover by using also an output of a demodulation circuit of the delay detection system just after a standby system is selected and selecting an output of a demodulation circuit of the synchronization detection system in the stage when the synchronization is estab lished CONSTITUTION:When a receiver 400b of a standby system is started, a demodulation circuit 9' of the synchronization detection system and a demodulation circuit 9'' of the delay detection system are respectively operated. A control circuit 20 controls the equipment to select an output of the demodulation circuit 9'' just after the standby system is selected and switches a changeover switch 11' to the position of the demodulation circuit 9' in the stage that the synchronization is established. Then a demodulation output of the demodulation circuit 9' is given to processing circuits after an error correction circuit decoder 10'. Thus, no out of synchronism takes place even in the presence of a momentary interruption or frequency deviation or the like at transmitters 100a, 100b by employing delay detection in the initial stage of the switching of the receiver 400b of the standby system and the receiver 400a of the active system and then the changeover of the receivers 400a, 400b is smoothly implemented.
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公开(公告)号：JPH04372247A
公开(公告)日：1992-12-25
申请号：JP15018791
申请日：1991-06-21
Applicant: TOSHIBA CORP
Inventor： FUJII YASUYUKI , TANAKA SHUICHI
Abstract: PURPOSE:To reduce the cost of a speed conversion circuit and to allow the MODEM to cope with even a fast signal speed of each channel sufficiently. CONSTITUTION:A device in which a 1st speed conversion means 103 adds a space for error correction code to a transmission signal, adds an error correction code to the result, modulates it and the modulated signal is transmitted. A reception signal is demodulated and processed based on the error correction code at an error correction processing means, the space for correction code is eliminated and the result is decoded into the original transmission signal, is provided with a 1st distribution means 102 distributing the transmission signal into plural series before the 1st speed conversion means, with a 1st series conversion means 106 restoring the plural series of the signals with an error correction code added thereto to the series before the distribution to form the modulation system. The demodulation system is provided with a 2nd distribution means distributing the demodulated reception signal into plural series and giving the result to an error correction processing means, a 2nd speed conversion means eliminating the space for the correction code from the signal after error correction processing and with a 2nd series conversion means restoring the plural series of signals after space is eliminated into the series before the distribution.
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公开(公告)号：JPH03140042A
公开(公告)日：1991-06-14
申请号：JP27719889
申请日：1989-10-26
Applicant: TOSHIBA CORP
Inventor： FUJII YASUYUKI , TANAKA SHUICHI
IPC: H04L27/36
Abstract: PURPOSE:To always minimize a carrier leakage without long time adjustment even when any temperature fluctuation takes place by cancelling a DC fluctuation component due to temperature included in positive and negative base band signals with common mode rejection action of a differential amplifier. CONSTITUTION:The circuit is provided with a D/A converter 25a having 2 bipolar output pairs and an n-bit digital signal is inputted to the D/A converter 25a to output positive and negative 2 analog base band signals in response to the input digital signal respectively. The positive and negative base band signals are inputted to an operational amplifier circuit 26a forming a differential amplifier, where they are subtracted together and a resulting output signal is inputted to one input of a couple of base band signal input terminals of a ring modulator 23a as an unbalanced input to modulate a carrier. Thus, carrier leakage is always minimized without adjustment for a long time even when any level of temperature fluctuation takes place.
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Patent Agency Ranking
公开(公告)号：JPH02266727A
公开(公告)日：1990-10-31
申请号：JP8872289
申请日：1989-04-07
Applicant: TOSHIBA CORP
Inventor： TANAKA SHUICHI
Abstract: PURPOSE:To perform an error correction processing for continuous plural bit errors as a one-bit error by providing plural error correction means, distribution input means, and synthetic output means at every in-phase component and orthogonal component of an input signal, respectively. CONSTITUTION:At an error correction circuit encoder part 70, a digital input signal is distributed and supplied to error correction circuit encoders 711a, 711b, and 71Qa, 71Qb at every bit alternately by serial-parallel(S/P) converters 721 and 72Q at every in-phase component DI and orthogonal component DQ. And an error correction encoding processing is applied on the signal at a state where it is separated to an odd bit string and an even bit string, and they are synthesized to a series of digital signal at every in-phase component and orthogonal component by P/S converters 731 and 73Q, respectively. In such a way, it is possible to perform the error correction processing for the continuous plural bit errors as the one-bit error even when they occur in the digital signal on a transmission line.
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公开(公告)号：JPH01173924A
公开(公告)日：1989-07-10
申请号：JP33050387
申请日：1987-12-26
Applicant: TOSHIBA CORP
Inventor： ENDO KENJIRO , TANAKA SHUICHI
Abstract: PURPOSE:To maintain a picture signal with high definition even when an interpolation processing is applied by forming the luminance signal of a picture sample as a high-order symbol, and the chrominance signal of the picture sample as a low-order symbol. CONSTITUTION:A sample word is constituted of 16 bits, and is divided into high-order 8 bits and low-order 8 bits, and the luminance signal Y is allocated to the high-order symbol and the chrominance signal C to the low-order symbol. Therefore, the luminance signal with sensible visibility is arranged to the high- order symbol (8 bits) of a word of 16 bits, and the chrominance signal with low visual sensitivity to the low-order symbol (8 bits). Therefore, in case of performing a corrective arithmetic operation, an interpolation signal can be obtained with at least accuracy of 7 bits from the luminance signal even when a carry is generated from a low-order. In such a way, it is possible to prevent fatal error data from being generated in the chrominance signal even by performing the interpolation processing, and an image with high definition can be obtained.
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公开(公告)号：JPS6488980A
公开(公告)日：1989-04-03
申请号：JP24401787
申请日：1987-09-30
Applicant: TOSHIBA CORP
Inventor： TANAKA SHUICHI , KAKIZAKI MIKIO
IPC: G11B27/02 , G11B27/034
Abstract: PURPOSE:To lighten the burden of an user at the time of edit by setting a reproducing time limit and a priority block, selecting a block having a longest addition time from reproduced data, eliminating track cut on the way of the block and reducing a blank part. CONSTITUTION:The reproducing time limit and the priority block are specified by a key 11 and stored in a memory 22. The operation signal of a key for editing is supplied to a block selection control part 27 and data in the memory 22 is read to a block length calculating part 28. The time length of each block is calculated and stored in the memory 22. The total time of these time length and the corresponding thing stored in the memory 22 is calculated 32 and set to the memory 22. Besides, the size of the time length of the block which is not specified is compared 2 and the time length of the block having the maximum value is selected 30. The longest time set to the memory 22 is made to be valid so far as it is not over a rest time and the longest time is subtracted from the rest time and set to the memory 22. Then a sequence control part 13 makes a CD reproducing part 14 based on the contents in the memory 22.
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公开(公告)号：JPS6488978A
公开(公告)日：1989-04-03
申请号：JP24401587
申请日：1987-09-30
Applicant: TOSHIBA CORP
Inventor： TANAKA SHUICHI
IPC: G11B27/02 , G11B27/034
Abstract: PURPOSE:To lighten the burden of an user at the time of edit by setting a reproducing time limit, selecting the longest time length of each block of reproduced data, eliminating track out on the way of the block and reducing a blank part. CONSTITUTION:The data of a disk 17 is supplied to a memory 22 from a CD reproducing part 14, the reproducing time limit is specified by a key 11 and set to the memory 22. Then, the operation signal of the edit key is given to a block selection control part 27 through a sequence control part 13, the program time of each block of the data in the memory 22 is calculated by a block length calculating part 28 and stored in the memory 22. Besides, the size of it is compared by a comparison arithmetic operation part 29, the program time of the block of the maximum value is selected by an arithmetic operation part 30 and stored in the memory 22. This longest time is made to be valid so far as it is not over the time limit, subtracted 31 from the rest time and stored in the memory 22 as an updated value. The control part 13 makes the reproducing part 14 to execute searching/reproducing operation based on the data in the memory 22.
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公开(公告)号：JPS63232627A
公开(公告)日：1988-09-28
申请号：JP6422487
申请日：1987-03-20
Applicant: TOSHIBA CORP
Inventor： OYA YASUNORI , TANAKA SHUICHI
IPC: H03M9/00
Abstract: PURPOSE:To convert stably data at a high speed by ANDing a clock signal of 4-series parallel data and a 2-multiple clock signal by a 1st 2-multiple means by means of an AND means so as to use the signal as a trigger pulse of a 4-bit shift register. CONSTITUTION:The 4-series parallel data shown in figure (a) fed to signal input terminals 1A-1D are ANDed with a timing signal of 4-series being an output signal of a shift register 3 by AND gates 2A-2D. A clock signal of a parallel data shown in figure (b) fed to a clock input terminal 4 and a signal shown in figure (c) being 2-multiple of the signal by a clock 2-multiple circuit 5A are used and ANDed by an AND gate 6 to obtain a signal shown in figure (d) from the timing signal. Then the result is used as a trigger pulse and inputted to the shift register 3 to give a 4-bit circulating function. Thus, even with a high speed shift register without any circulating function in use, the 4-series parallel data of 16QAM system is converted into a serial data of one series stably at a high speed with simple circuit constitution.
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