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    Static random access memory unit cell structure and static random access memory unit cell layout structure
    51.
    发明授权
    Static random access memory unit cell structure and static random access memory unit cell layout structure 有权
    静态随机存取单元单元格结构和静态随机存取单元布局结构

    公开(公告)号：US09196352B2

    公开(公告)日：2015-11-24

    申请号：US13776589

    申请日：2013-02-25

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Ching-Wen Hung ,  Po-Chao Tsao ,  Shu-Ru Wang ,  Chia-Wei Huang ,  Chieh-Te Chen ,  Feng-Yi Chang ,  Chih-Sen Huang

    IPC: H01L21/70 ,  G11C11/00 ,  G11C11/412 ,  H01L27/02 ,  H01L27/11

    CPC classification number: G11C11/412 ,  H01L27/0207 ,  H01L27/1104

    Abstract: A static random access memory unit cell layout structure is disclosed, in which a slot contact is disposed on one active area and another one across from the one. A static random access memory unit cell structure and a method of fabricating the same are also disclosed, in which, a slot contact is disposed on drains of a pull-up transistor and a pull-down transistor, and a metal-zero interconnect is disposed on the slot contact and a gate line of another pull-up transistor. Accordingly, there is not an intersection of vertical and horizontal metal-zero interconnects, and there is no place suffering from twice etching. Leakage junction due to stitch recess can be avoided.

    Abstract translation: 公开了一种静态随机存取存储器单元布局结构，其中，槽触点设置在一个有源区上，另一个位于一个有源区上。 还公开了一种静态随机存取存储单元单元结构及其制造方法，其中，在上拉晶体管和下拉晶体管的漏极上设置一个槽触点，并且设置金属零互连 在槽触点和另一个上拉晶体管的栅极线上。 因此，没有垂直和水平的金属零互连，没有两次蚀刻的地方。 可以避免缝合凹陷引起的泄漏接头。

    SEMICONDUCTOR PROCESS
    52.
    发明申请
    SEMICONDUCTOR PROCESS 有权
    半导体工艺

    公开(公告)号：US20150270261A1

    公开(公告)日：2015-09-24

    申请号：US14730230

    申请日：2015-06-03

    Applicant: United Microelectronics Corp.

    Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Po-Chao Tsao

    IPC: H01L27/06 ,  H01L21/768 ,  H01L29/40 ,  H01L49/02 ,  H01L29/66

    CPC classification number: H01L27/0629 ,  H01L21/28 ,  H01L21/76802 ,  H01L21/76877 ,  H01L27/1085 ,  H01L28/60 ,  H01L28/75 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/66477 ,  H01L29/66545

    Abstract: A semiconductor structure includes a metal gate, a second dielectric layer and a contact plug. The metal gate is located on a substrate and in a first dielectric layer, wherein the metal gate includes a work function metal layer having a U-shaped cross-sectional profile and a low resistivity material located on the work function metal layer. The second dielectric layer is located on the metal gate and the first dielectric layer. The contact plug is located on the second dielectric layer and in a third dielectric layer, thereby a capacitor is formed. Moreover, the present invention also provides a semiconductor process forming said semiconductor structure.

    Abstract translation: 半导体结构包括金属栅极，第二电介质层和接触插塞。 金属栅极位于基板和第一电介质层中，其中金属栅极包括具有U形横截面轮廓的功函数金属层和位于功函数金属层上的低电阻率材料。 第二电介质层位于金属栅极和第一电介质层上。 接触塞位于第二电介质层上，在第三电介质层中形成电容器。 此外，本发明还提供了形成所述半导体结构的半导体工艺。

    SEMICONDUCTOR DEVICE
    54.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20150108553A1

    公开(公告)日：2015-04-23

    申请号：US14583211

    申请日：2014-12-26

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Ling-Chun Chou ,  I-Chang Wang ,  Ching-Wen Hung

    IPC: H01L29/78 ,  H01L29/66

    CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834

    Abstract: A manufacturing method for a semiconductor device includes providing a substrate having at least agate structure formed thereon and a first spacer formed on sidewalls of the gate structure, performing an ion implantation to implant dopants into the substrate, forming a disposal spacer having at least a carbon-containing layer on the sidewalls of the gate structure, the carbon-containing layer contacting the first spacer, and performing a thermal treatment to form a protecting layer between the carbon-containing layer and the first spacer.

    Abstract translation: 一种用于半导体器件的制造方法，包括提供至少具有玛瑙结构的基板和形成在栅极结构的侧壁上的第一间隔物，进行离子注入以将掺杂剂注入衬底中，形成具有至少一个碳 所述含碳层与所述第一间隔物接触，并进行热处理以在所述含碳层和所述第一间隔物之间​​形成保护层。

    Method for forming semiconductor structure having metal connection
    55.
    发明授权
    Method for forming semiconductor structure having metal connection 有权
    用于形成具有金属连接的半导体结构的方法

    公开(公告)号：US08785283B2

    公开(公告)日：2014-07-22

    申请号：US13705183

    申请日：2012-12-05

    Applicant: United Microelectronics Corp.

    Inventor： Chieh-Te Chen ,  Feng-Yi Chang ,  Chih-Sen Huang ,  Ching-Wen Hung ,  Ching-Pin Hsu

    IPC: H01L21/336 ,  H01L29/66

    CPC classification number: H01L21/76816 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The present invention provides a method for forming a semiconductor structure having a metal connect. A substrate is provided, and a transistor and a first ILD layer are formed thereon. A first contact plug is formed in the first ILD layer to electrically connect the source/drain region. A second ILD layer and a third ILD layer are formed on the first ILD layer. A first opening above the gate and a second opening above the first contact plug are formed, wherein a depth of the first contact plug is deeper than that of the second opening. Next, the first opening and the second opening are deepened. Lastly, a metal layer is filled into the first opening and the second opening to respectively form a first metal connect and a second metal connect.

    Abstract translation: 本发明提供一种形成具有金属连接的半导体结构的方法。 提供衬底，并在其上形成晶体管和第一ILD层。 第一接触插塞形成在第一ILD层中以电连接源极/漏极区域。 在第一ILD层上形成第二ILD层和第三ILD层。 形成在栅极上方的第一开口和在第一接触插塞上方的第二开口，其中第一接触插塞的深度比第二开口的深度深。 接下来，加深第一开口和第二开口。 最后，将金属层填充到第一开口和第二开口中，以分别形成第一金属连接和第二金属连接。

    Method for fabricating fin-shaped field-effect transistor
    56.
    发明授权
    Method for fabricating fin-shaped field-effect transistor 有权
    制造鳍状场效应晶体管的方法

    公开(公告)号：US08765546B1

    公开(公告)日：2014-07-01

    申请号：US13925812

    申请日：2013-06-24

    Applicant: United Microelectronics Corp.

    Inventor： Ching-Wen Hung ,  Jia-Rong Wu ,  Chih-Sen Huang

    IPC: H01L27/088

    CPC classification number: H01L21/823431

    Abstract: A method for fabricating fin-shaped field-effect transistor (FinFET) is disclosed. The method includes the steps of: providing a substrate; forming a fin-shaped structure on the substrate; forming a first gate structure on the fin-shaped structure; forming a first epitaxial layer in the fin-shaped structure adjacent to the first gate structure; forming an interlayer dielectric layer on the first gate structure and the first epitaxial layer; forming an opening in the interlayer dielectric layer to expose the first epitaxial layer; forming a silicon cap on the first epitaxial layer; and forming a contact plug in the opening.

    Abstract translation: 公开了一种用于制造鳍状场效应晶体管（FinFET）的方法。 该方法包括以下步骤：提供衬底; 在基板上形成翅片状结构; 在所述鳍状结构上形成第一栅极结构; 在与所述第一栅极结构相邻的所述鳍状结构中形成第一外延层; 在所述第一栅极结构和所述第一外延层上形成层间电介质层; 在所述层间电介质层中形成开口以暴露所述第一外延层; 在所述第一外延层上形成硅帽; 并在开口中形成接触塞。

    Semiconductor device and method for fabricating the same
    60.
    发明授权
    Semiconductor device and method for fabricating the same 有权

    公开(公告)号：US11864469B2

    公开(公告)日：2024-01-02

    申请号：US17902895

    申请日：2022-09-05

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Ching-Wen Hung ,  Ya-Sheng Feng

    IPC: H10N50/80 ,  H01L21/768 ,  H10N50/01

    CPC classification number: H10N50/80 ,  H01L21/76801 ,  H01L21/76838 ,  H10N50/01

    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a metal interconnection in the first IMD layer; forming a bottom electrode layer and a pinned layer on the first IMD layer; forming a sacrificial layer on the pinned layer; patterning the sacrificial layer, the pinned layer, and the bottom electrode layer to form a first magnetic tunneling junction (MTJ); forming a second IMD layer around the first MTJ; removing the sacrificial layer to form a recess; forming a barrier layer and a free layer in the recess; forming a top electrode layer on the free layer; and patterning the top electrode layer and the free layer to form a second MTJ.

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