DIGITAL COLOR VIDEO IMAGE ENHANCEMENT FOR A RANDOM DITHER CIRCUIT

    公开(公告)号:CA2108851C

    公开(公告)日:1998-06-23

    申请号:CA2108851

    申请日:1993-10-20

    Inventor: LUM SANFORD S

    Abstract: The present invention relates to a method of enhancing a digital color video image comprised of separating a source pixel into individual component parts, for each component part, generating a random number having the same length as the corresponding component part, adding each random number to its corresponding component part to form resultant component parts, and combining the resultant component parts to form a destination pixel.

    GRAPHICS DISPLAY SYSTEM
    62.
    发明专利

    公开(公告)号:CA2070934C

    公开(公告)日:1998-05-05

    申请号:CA2070934

    申请日:1992-06-10

    Abstract: A graphics display system for a computer comprising a display memory having a DRAM port and a serial port, a video controller including a host graphics controller having a bus port, a lookup table and a digital-to-analog converter for receiving lookup table data from the lookup table and converting it into signals reproducible by a display, the DRAM and serial ports being multiplexed to a combined bus, the combined bus being connected to the bus port of the graphics controller, the lookup table having an input for receiving data from the combined bus, apparatus; fur causing passage of serial data along the bus from the display memory in higher priority than any other data for provision of display data to the lookup table whereby the lookup table can provide the lookup table data to the digital-to-analog converter.

    FLAG-BASED HIGH-SPEED I/O DATA TRANSFER

    公开(公告)号:CA2140963C

    公开(公告)日:1997-12-16

    申请号:CA2140963

    申请日:1995-01-24

    Inventor: VARGA GABRIEL

    Abstract: A memory address pointer that selects a memory location that is mapped to a video graphics circuit port is incremented only when all bytes in a memory location have been read from or written to by the host CPU. This does not depend on the order in which the host CPU reads or writes data bytes. Therefore a video controller that uses the present invention will work with 8 bit, 16 bit as well as high performance 32 bit input/output instructions.

    PLACEMENT OF MEMORY MAPPED REGISTERS AT CONSECUTIVE ADDRESSES

    公开(公告)号:CA2140958A1

    公开(公告)日:1996-03-27

    申请号:CA2140958

    申请日:1995-01-24

    Abstract: A method of moving data into a peripheral system of a computer from a CPU comprised of connecting a port of a memory mapped register of the system to a memory bus of the computer, connecting a port of a CPU to an I/O bus to which at least one peripheral is connected, and connecting a memory access port of the CPU to the memory bus, memory mapping a register of the CPU to multiple consecutive addresses, and applying a repetitive memory data move command to the processor to transfer data into the register of the system through the port of the register of the system via the memory bus from the register of the CPU.

    Universal CD-ROM Interface
    68.
    发明专利

    公开(公告)号:CA2122079A1

    公开(公告)日:1995-08-17

    申请号:CA2122079

    申请日:1994-04-25

    Abstract: The present invention relates to a universal peripheral interface comprised of control logic circuits for a plurality of peripherals carrying different signals on different pins of respective peripheral connectors, a single interface connector for mating with any of the peripheral connectors, a first multiplexer for interfacing any of the control logic circuits with the single interface connector and for switching particular lines of each of the control logic circuits carrying particular signals to particular pins of the single connector, and apparatus for controlling the multiplexer to map the lines to the particular pins of the single connector.

    Video Processing Unit
    70.
    发明专利

    公开(公告)号:CA2113600A1

    公开(公告)日:1995-03-31

    申请号:CA2113600

    申请日:1994-01-17

    Abstract: The present invention relates to a video display processor comprised apparatus for receiving digital input signal components of a signal to be displayed, apparatus for converting the components to a desired format, apparatus for scaling and blending the signals in the desired format, apparatus for outputting the scaled and blended signals for display or further processing, and an arbiter and local timing apparatus for controlling the apparatus substantially independently of a host CPU.

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