公开(公告)号：GB2217061A

公开(公告)日：1989-10-18

申请号：GB8806861

申请日：1988-03-23

Applicant: BENCHMARK TECHNOLOGIES

Inventor： TREVETT NEIL FRANCIS ,  WILSON MALCOLM ERIC

IPC: G06F9/26 ,  G06F11/34 ,  G06F11/36

Abstract: A computer system with an architectural feature which permits debugging. This system includes "claw" logic. The claw logic claws back control to the monitor task after one instruction in the user task has been run. The instruction which returns control to the user task requests a claw interrupt. This is delayed by one cycle so that the interrupt occurs on the first instruction executed in the user task. So control is restored to the monitor task before the second instruction in the user task is executed. This means that the monitor process (used during debugging) can single-step the application program, without the monitor program itself having to be single-stepped.

公开(公告)号：GB2217060A

公开(公告)日：1989-10-18

申请号：GB8806860

申请日：1988-03-23

Applicant: BENCHMARK TECHNOLOGIES

Inventor： BALDWIN DAVID ROBERT ,  AHISHALILAR YAVUZ

IPC: G06F9/38 ,  G06F15/78

Abstract: A processing subsystem which includes at least four processors, all concurrently operable, including a control processor 110, a data transfer processor 120, and at least two general-purpose numeric processors 130, connected in parallel on a very wide cache bus 144. The numeric processors are commanded by the control processor to execute respective sequences of instructions, but operate asynchronously with the control processor.

公开(公告)号：GB2217056A

公开(公告)日：1989-10-18

申请号：GB8806856

申请日：1988-03-23

Applicant: BENCHMARK TECHNOLOGIES

Inventor： BALDWIN DAVID ROBERT

IPC: G06F9/38 ,  G06F15/78

Abstract: A dual port memory 430 is used, partitioned in software so that the top half of the memory is allocated to the control processor, (110) and the bottom half to the floating point is processor (130). This allocation is switched when both processors set respective flag bits indicating that they are ready to switch. On accesses to this memory, additional bits tag the access as "physical," "logical," or "preview". A physical access is interpreted as a literal address within the full memory, and the double buffering is ignored. A logical access is supplemented by an additional address bit, determined by the double buffering switch state. A preview access is used for read access only, and goes to the opposite bank of memory from that which would be accessed in a logical access. The use of preview can be particularly advantageous in avoiding data flow inefficiencies at synchronization points in pipelined algorithms. Preferably double buffering is used in a register file at the interface between the numeric processor and the large data cache memory (140) in the multiprocessor system. The partitioning of the register file avoids data collisions in the cache memory.

公开(公告)号：GB2215960A

公开(公告)日：1989-09-27

申请号：GB8806879

申请日：1988-03-23

Applicant: BENCHMARK TECHNOLOGIES

Inventor： TREVETT NEIL FRANCIS ,  WILSON MALCOLM ERIC ,  LLOYD SARAH JANE

IPC: G06F17/17 ,  G06T15/10 ,  G06T15/87 ,  G09G5/20

Abstract: A method of linear interpolation over a line having a given length comprising the steps of initializing the multiplier accumulators output registers with predetermined initial values 410, 412 [e.g. with the initial rounding value and the starting value for one of the coordinates (e.g. Y), respectively]; loading a first input register 402 of the multiplier accumulator with a value equal to the incremental change (e.g. DELTA Y=5) in the output value over the length of the line; loading a second input register 404 of the multiplier accumulator with a value (1/N) equal to the reciprocal of the length of the line (N); causing the multiplier 406 to multiply the values (eg DELTA Y and 1/N) at its first and second inputs; accumulating the fractional part of the result of the multiplication in a first output register 410; accumulating the interger part of the result of the multiplication added with the overflow of the first output register in a second output register, 412, whereby and accumulated result is formed. The overflow is accumulated in a third output register, 414, and overflows to the integral register. For Gouraud shading of a line, one of the input registers is loaded with colour change along a line and the other with reciprocal of line length. An output register, 412, is initialised with a start colour.

公开(公告)号：GB2215952A

公开(公告)日：1989-09-27

申请号：GB8806845

申请日：1988-03-23

Applicant: BENCHMARK TECHNOLOGIES

Inventor： TREVETT NEIL FRANCIS ,  WILSON MALCOLM ERIC

IPC: G06T1/20

Abstract: The system and method of the present invention performs raster operations in a patch access environment using two or more source patches to produce an X and/or Y shifted destination patch. More than one X and/or Y shifted destination patches may be produced by the present invention to provide the desired X and/or Y shift and merge of the source image. Several embodiments of the present invention can process two planes of patch data in one memory cycle by using lime domain multiplexing (TDM). In one embodiment, this TDM capability allows for patch planes to be shifted and/or merged in an efficient manner. In another embodiment, this allows for patch plane substitution within and across patches, and for manipulation between and within patch planes. The inventors have taken advantage of the fact that the elements of the present apparatus can be function at a rate which is faster than the image memory.

公开(公告)号：GB2215883A

公开(公告)日：1989-09-27

申请号：GB8806868

申请日：1988-03-23

Applicant: BENCHMARK TECHNOLOGIES

Inventor： BALDWIN DAVID ROBERT

IPC: G06F9/24 ,  G06F12/08 ,  G06F12/0886

Abstract: A processing sub-system of the system includes concurrently asynchronously operable processors including a numerical processor, 130, and a cable memory 140 having a storage capacity of at least one megabyte and which is more than sixty-four bits wide. The interface between processor and cache includes a set of multiple registers in parallel, each one word wide. The registers provide parallel interface to cache and serial to a respective processor. Each register connects to a respective processor. Each register connects to a respective enable line. The architective allow processors to conduct parallel read write operations to cache. The separate enable line allow selectable masking of parallel write operations so that read-modify-write cycles are not necessary.

公开(公告)号：GB2215882A

公开(公告)日：1989-09-27

申请号：GB8806867

申请日：1988-03-23

Applicant: BENCHMARK TECHNOLOGIES

Inventor： BALDWIN DAVID ROBERT

IPC: G06F9/22

Abstract: A multiprocessor system, where a control processor 110 controls all data transfers to and from a numeric processing module 130, and the control processor executes essentially the same microcode for essentially all operations (by the numeric processor) of a given formal type. For example, vector adds, vector subtracts, and vector multiplies are all didactic operations, i.e. they map two vectors onto a third vector, and have common control processor microcode although the numeric processor microcode varies according to the operation performed.

公开(公告)号：GB2215879A

公开(公告)日：1989-09-27

申请号：GB8806853

申请日：1988-03-23

Applicant: BENCHMARK TECHNOLOGIES

Inventor： BALDWIN DAVID ROBERT

IPC: G06F9/22

Abstract: A numeric processing portion, of a multiprocessor subsystem, which uses compacted microcode. A bypass register is used to permit selected bits in microcode instruction fields to be replaced, when the instruction is called from writable control storage, 220 by other bits passed down from a higher-level processor. Instruction decode logic 260 is connected to receive and decode microcoded instructions called by program counter logic from the program memory. The decode logic combines an operation specifier read from an instruction register with a microinstruction called from the program memory to provide a complete microinstruction for execution.

公开(公告)号：GB2215877A

公开(公告)日：1989-09-27

申请号：GB8806851

申请日：1988-03-23

Applicant: BENCHMARK TECHNOLOGIES

Inventor： BALDWIN DAVID ROBERT

IPC: G06F9/38 ,  G06F15/78

Abstract: A processing subsystem which includes one or more numeric processors, 130, and also at least one application-customized processor. The application-customized processor is particular adapted for some particular class of operations, such as discrete Fourier transform operations, and the numeric processor provides acceptably high speed on the general range of numeric computations. A control processor, 110 runs concurrently to the other processors, and can perform many tasks invisibly to them (such as address calculation and data transfer). Preferably a separate data transfer processor 120 is used, which handles external interface needs, and which also runs concurrently in background to the numeric and application-specific processors.

公开(公告)号：GB2215873A

公开(公告)日：1989-09-27

申请号：GB8806835

申请日：1988-03-23

Applicant: BENCHMARK TECHNOLOGIES

Inventor： TREVETT NEIL FRANCIS ,  WILSON MALCOLM ERIC

IPC: G06F15/17