公开(公告)号：US11107932B2

公开(公告)日：2021-08-31

申请号：US16586697

申请日：2019-09-27

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huilong Zhu

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/775 ,  H01L29/10 ,  B82Y10/00 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49

Abstract: There are provided a nanometer semiconductor device with a high-quality epitaxial layer and a method of manufacturing the same. According to an embodiment, the semiconductor device may include: a substrate; at least one nanowire spaced apart from the substrate; at least one semiconductor layer, each formed around a periphery of respective one of the at least one nanowire to at least partially surround the corresponding nanowire, wherein the semiconductor layer(s) formed around the respective nanowire(s) are separated from each other; an isolation layer formed on the substrate, exposing the at least one semiconductor layer; and a gate stack formed on the isolation layer and intersecting the at least one semiconductor layer, wherein the gate stack includes a gate dielectric layer at least partially surrounding a periphery of respective one of the at least one semiconductor layer and a gate conductor layer.

公开(公告)号：US11081484B2

公开(公告)日：2021-08-03

申请号：US16810223

申请日：2020-03-05

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huilong Zhu ,  Zhengyong Zhu

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/285 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/8238 ,  H01L29/06

Abstract: There are provided an Integrated Circuit (IC) unit, a method of manufacturing the same, and an electronic device including the IC unit. According to an embodiment, the IC unit includes a first source/drain layer, a channel layer and a second source/drain layer for a first device and a first source/drain layer, a channel layer and a second source/drain layer for a second device stacked in sequence on a substrate. In the first device, the channel layer includes a first portion and a second portion separated from each other. The first source/rain layer and the second source/drain layer each extend integrally to overlap both the first portion and the second portion of the channel layer. The IC unit further includes a first gate stack surrounding a periphery of the first portion and also a periphery of the second portion of the channel layer of the first device, and a second gate stack surrounding a periphery of the channel layer of the second device.

公开(公告)号：US11056580B2

公开(公告)日：2021-07-06

申请号：US15757601

申请日：2015-11-23

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Tianchun Ye

IPC: H01L21/02 ,  H01L29/66 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11568

Abstract: A semiconductor device comprise a substrate, source/drain regions, a channel region, a gate dielectric layer and a gate conductive layer, wherein the gate dielectric layer comprises a barrier layer, a storage layer, a first interface layer, a tunneling layer, a second interface layer. In accordance with the semiconductor device and the manufacturing method of the present invention, an interface layer is added between the storage layer and tunneling layer in the gate dielectric by adjusting process step, and the peak concentration and peak location of nitrogen can be flexibly adjusted, effectively improving the quality of the interface between the storage layer and the tunneling layer in the gate dielectric layer, increasing process flexibility, improving device reliability and current characteristics.

公开(公告)号：US20210175366A1

公开(公告)日：2021-06-10

申请号：US17112903

申请日：2020-12-04

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong Zhu

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/78

Abstract: A C-shaped active area semiconductor device and a method of manufacturing the same and electronic device including the semiconductor device are provided. According to embodiments, the semiconductor device includes: a channel portion extending vertically on a substrate; source/drain portions located at upper and lower ends of the channel portion relative to the substrate and along the channel portion, wherein the source/drain portion extends toward a side of the channel portion in a lateral direction relative to the substrate, so that the source/drain portions and the channel portion constitute a C-shaped structure; a gate stack that overlaps the channel portion on an inner sidewall of the C-shaped structure, wherein the gate stack has a portion surrounded by the C-shaped structure; and a back gate stack overlapping the channel portion on an outer sidewall of the C-shaped structure.

公开(公告)号：US20210175355A1

公开(公告)日：2021-06-10

申请号：US17110630

申请日：2020-12-03

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong ZHU

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66

Abstract: A semiconductor device with a U-shaped channel and a manufacturing method thereof and an electronic apparatus including the semiconductor device are disclosed. According to embodiments, the semiconductor device may include: a channel portion extending vertically on a substrate and having a U-shape in a plan view; source/drain portions located at upper and lower ends of the channel portion and along the U-shaped channel portion; and a gate stack overlapping the channel portion on an inner side of the U shape.

公开(公告)号：US11024708B1

公开(公告)日：2021-06-01

申请号：US16824761

申请日：2020-03-20

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Yongliang Li ,  Xiaohong Cheng ,  Qingzhu Zhang ,  Huaxiang Yin ,  Wenwu Wang

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/088

Abstract: A semiconductor device, including: a silicon substrate; multiple fin structures, formed on the silicon substrate, where each extends along a first direction; a shallow trench insulator, located among the multiple fin structures; a gate stack, intersecting with the multiple fin structures and extending along a second direction, where first spacers are formed on two sidewalls in the first direction of the gate stack; source-or-drain regions, formed on the multiple fin structures, and located at two sides of the gate stack along the first direction; and a channel region, including a portion of the multiple fin structures located between the first spacers. and notch structures. A notch structure recessed inward is located between each of the multiple fin structures and the silicon substrate. The notch structure includes an isolator that isolates each of the multiple fin structures from the silicon substrate.

公开(公告)号：US10978591B2

公开(公告)日：2021-04-13

申请号：US16060399

申请日：2016-06-27

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong Zhu

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  B82Y10/00 ,  H01L29/66 ,  H01L29/786 ,  H01L21/02 ,  H01L29/165 ,  H01L29/267

Abstract: A nanowire semiconductor device having a high-quality epitaxial layer. The semiconductor device may include: a substrate; one or more nanowires spaced apart from the substrate, wherein the nanowires each extend along a curved longitudinal extending direction; and one or more semiconductor layers formed around peripheries of the respective nanowires to at least partially surround the respective nanowires, wherein the respective semiconductor layers around the respective nanowires are spaced apart from each other.

公开(公告)号：US10978470B2

公开(公告)日：2021-04-13

申请号：US16338212

申请日：2017-03-31

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong Zhu

IPC: H01L27/11582 ,  H01L29/78 ,  H01L21/28 ,  H01L21/02 ,  H01L21/306 ,  H01L27/11514 ,  H01L27/11556 ,  H01L29/04 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792

Abstract: The memory device includes multiple stacked layers of memory cells. Each of the layers includes a first array of first memory cells and a second array of second memory cells, which are nested with each other. The first memory cells and the second memory cells in the respective layers are substantially aligned to each other in a stacking direction of the memory cell layers. Each of the first memory cells is a vertical device based on a first source/drain layer, a channel layer, and a second source/drain layer stacked. Each of the second memory cells is a vertical device based on an active semiconductor layer extending in the stacking direction. The first and second memory cells include respective storage gate stacks, which share a common gate conductor layer. Gate conductor layers in the same memory cell layer are integral with each other.

公开(公告)号：US10964529B2

公开(公告)日：2021-03-30

申请号：US15300925

申请日：2014-04-17

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Dongmei Li ,  Lei Zhou ,  Shengfa Liang ,  Xiaojing Li ,  Hao Zhang ,  Changqing Xie ,  Ming Liu

IPC: H01L21/02 ,  B08B3/12 ,  C11D11/00 ,  C11D7/06 ,  C11D7/08 ,  C11D3/39 ,  C11D7/10

Abstract: The present disclosure provides a method for cleaning a lanthanum gallium silicate wafer which comprises the following steps: at a step of 1, a cleaning solution constituted of phosphorous acid, hydrogen peroxide and deionized water is utilized to clean the lanthanum gallium silicate wafer with a megahertz sound wave; at a step of 2, the cleaned lanthanum gallium silicate wafer is rinsed and dried by spinning; at a step of 3, a cleaning solution constituted of ammonia, hydrogen peroxide and deionized water is utilized to clean the lanthanum gallium silicate wafer with the megahertz sound wave; at a step of 4, the cleaned lanthanum gallium silicate wafer is rinsed and dried by spinning; and at a step of 5, the rinsed and dried wafer is placed in an oven to be baked. The present invention shortens a period of acidic cleaning process and prolongs a period of alkaline cleaning and utilizes a more effective cleaning with megahertz sound wave to replace the conventional ultrasonic cleaning to solve the issue of cleaning the lanthanum gallium silicate wafer after a cutting process and to improve surface cleanliness of the lanthanum gallium silicate wafer to get a better cleaning effect.

公开(公告)号：US10958261B2

公开(公告)日：2021-03-23

申请号：US16495485

申请日：2017-03-20

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Zhi Li ,  Jianzhong Zhao ,  Yumei Zhou ,  Weihua Xin

IPC: H03K9/08 ,  H02M1/096

Abstract: The present disclosure provides a serial PWM signal decoding circuit based on a capacitor charge-discharge structure, comprising: a timing logic generation circuit configured to receive, at an input end of the timing logic generation circuit, a PWM differential signal, and generate a timing logic signal; and at least two capacitor charge-discharge decoding modules, each of the at least two capacitor charge-discharge decoding modules has an input end connected to an output end of the timing logic generation circuit, and is configured to perform charging and discharging based on the timing logic signal. During a decoding process, a voltage at a charge-discharge capacitor of the capacitor charge-discharge decoding module before the charging and discharging is a common mode voltage VCM, and a voltage at a charge-discharge node after the end of the charging and discharging is a voltage VC, and the PWM signal is decoded by identify the PWM signal through determining a polarity of a voltage difference between the common mode voltage VCM and the voltage VC. The present disclosure further provides a method of decoding based on a capacitor charge-discharge structure. The present disclosure provides a simple structure and does not need synchronize code streams, thus avoiding the use of a complicated CDR and an oversampling structure, realizing the decoding of PWM signals at different rates, increasing the efficiency of signal transmission and lowering the power consumption.