公开(公告)号：US20250089272A1

公开(公告)日：2025-03-13

申请号：US18957839

申请日：2024-11-24

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Ying-Cheng CHUANG

IPC: H10B99/00 ,  H10B12/00

Abstract: A semiconductor memory device manufacturing method includes: sequentially forming a lower oxide layer, a word line metal layer and an upper oxide layer over at least a portion of a memory cell; forming a through hole passing through the upper oxide layer, the word line metal layer and the lower oxide layer to expose the portion of the memory cell; forming a sacrificial pillar into the through hole; removing the upper oxide layer to expose a top portion of the sacrificial pillar; sequentially forming a first oxide spacer sidewall, a nitride spacer sidewall and a second oxide spacer sidewall on a sidewall of the top portion of the sacrificial pillar; removing the nitride spacer sidewall to form a void gap; etching the word line metal layer through the void gap to form separate word lines.

公开(公告)号：US20250089243A1

公开(公告)日：2025-03-13

申请号：US18961425

申请日：2024-11-26

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Tseng-Fu LU

IPC: H10B12/00 ,  H01L21/308 ,  H01L21/762

Abstract: A memory structure includes a substrate, an isolation area, a plurality of active areas and a first word line. The isolation area and the active areas are formed on the substrate. The isolation area surrounds the active areas, and the isolation area comprises an isolation structure formed in an isolation trench recessed in the isolation area. The first word line is formed across a first active area of the active areas and the isolation area. The first word line has a first width in the first active area and a second width in the isolation area. The first width is less than the second width.

公开(公告)号：US20250089241A1

公开(公告)日：2025-03-13

申请号：US18464287

申请日：2023-09-11

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Jhen-Yu TSAI

IPC: H10B12/00

Abstract: A memory device includes a substrate, a capacitor, a transistor, a word line, a bit line contact and a body contact. The capacitor is over the substrate. The transistor is over the capacitor, and the transistor includes a channel region, a gate over the channel region, and a source and a drain on opposite sides of the channel region, in which the drain is over the capacitor. The word line is over and electrically connected to the gate of the transistor. The bit line contact is over and electrically connected to the source of the transistor. The body contact is below the source of the transistor.

公开(公告)号：US12250806B2

公开(公告)日：2025-03-11

申请号：US18509601

申请日：2023-11-15

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Hung-Chi Tsai

IPC: H10B12/00

Abstract: The present disclosure relates to a semiconductor device including a semiconductor substrate, word lines, mask layers, spacers, a conductive plug, a conductive cap layer, and a dielectric layer. The word lines are disposed over the semiconductor substrate. The mask layers are disposed over the plurality of word line, respectively. The spacers are disposed over opposite sidewalls of the word lines and opposite sidewalls of the mask layers, respectively. The conductive plug is disposed between the word lines. The conductive cap layer is disposed over the conductive plug. The dielectric layer is disposed over the word lines and the spacers. Each of the spacers includes an inner spacer, an outer spacer, and an air gap. The inner spacer is in contact with the respective word line and the respective mask layer. The air gap is disposed between the inner spacer and the outer spacer.

公开(公告)号：US12249512B2

公开(公告)日：2025-03-11

申请号：US18749899

申请日：2024-06-21

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Jar-Ming Ho

IPC: H01L21/00 ,  H01L21/285 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/532 ,  H01L23/544 ,  H10B12/00

Abstract: The present disclosure provides a semiconductor structure, which includes: a first conductive layer arranged over a substrate; a dielectric layer arranged over the first conductive layer; a plurality of first conductive plugs penetrating through the dielectric layer; a plurality of spacers surrounding the respective first conductive plugs; a lining layer covering the dielectric layer, the spacer and the first conductive plugs, wherein the lining layer and the first conductive plugs include manganese (Mn); a second conductive plug penetrating through the lining layer; and a second conductive layer over the lining layer and the second conductive plug.

公开(公告)号：US20250081591A1

公开(公告)日：2025-03-06

申请号：US18511039

申请日：2023-11-16

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： YING-CHENG CHUANG

IPC: H01L27/08 ,  H01L21/8234

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate including a first peripheral region and a second peripheral region; a plurality of recessed gates respectively including a recessed gate dielectric layer inwardly positioned in the first peripheral region and including a U-shaped cross-sectional profile, a recessed gate bottom conductive layer positioned on the recessed gate dielectric layer and including a valley-shaped cross-sectional profile, resulting in a first valley, a recessed gate top conductive layer conformally positioned on the first valley of the recessed gate bottom conductive layer, and a recessed gate capping layer positioned on the recessed gate top conductive layer; and a peripheral gate structure positioned on the second peripheral region. An element density of the first peripheral region is greater than an element density of the second peripheral region.

公开(公告)号：US20250081479A1

公开(公告)日：2025-03-06

申请号：US18242076

申请日：2023-09-05

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： HSIH-YANG CHIU

IPC: H10N70/00

Abstract: A semiconductor device includes a bottom electrode structure disposed over a semiconductor substrate. The bottom electrode structure includes a first metal layer, a second metal layer, a third metal layer, a fourth metal layer, and a fifth metal layer from bottom to top. The first metal layer, the third metal layer and the fifth metal layer include a first metal material, and the second metal layer and the fourth metal layer include a second metal material different from the first metal material. The semiconductor device also includes a high-k dielectric structure disposed on opposite sidewalls of the bottom electrode structure. The opposite sidewalls of the bottom electrode structure are step-shaped. The semiconductor device further includes a top electrode structure laterally surrounding the bottom electrode structure and separated from the bottom electrode structure by the high-k dielectric structure.

公开(公告)号：US20250081439A1

公开(公告)日：2025-03-06

申请号：US18511055

申请日：2023-11-16

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： CHIH-WEI HUANG

IPC: H10B12/00 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device structure includes a semiconductor substrate, a first fin structure, a first S/D structure, and a bit line contact. The first fin structure is protruding from the semiconductor substrate, and has a first sidewall, a second sidewall, and a top surface connecting the first sidewall to the second sidewall. The first S/D structure is disposed over the first fin structure, and covering the top surface, a portion of the first sidewall, and a portion of the second sidewall of the first fin structure. The bit line contact is disposed over the first S/D structure. The bit line contact includes a barrier layer in contact with the first S/D structure and a conductive layer disposed over the barrier layer.

公开(公告)号：US20250081438A1

公开(公告)日：2025-03-06

申请号：US18241057

申请日：2023-08-31

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： CHIH-WEI HUANG

IPC: H10B12/00 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device structure includes a semiconductor substrate, a first fin structure, a first S/D structure, and a bit line contact. The first fin structure is protruding from the semiconductor substrate, and have a first sidewall, a second sidewall, and a top surface connecting the first sidewall to the second sidewall. The first S/D structure is disposed over the first fin structure, and covering the top surface, a portion of the first sidewall, and a portion of the second sidewall of the first fin structure. The bit line contact is disposed over the first S/D structure. The bit line contact includes a barrier layer in contact with the first S/D structure and a conductive layer disposed over the barrier layer.

公开(公告)号：US12245431B2

公开(公告)日：2025-03-04

申请号：US18383146

申请日：2023-10-24

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Yuan-Yuan Lin

IPC: H10B43/27 ,  H01L21/768 ,  H01L23/532 ,  H01L21/02 ,  H01L21/311 ,  H01L23/522

Abstract: The present disclosure provides a vertical memory structure including a semiconductor stack, a contact plug, gate electrodes and air gap structures. The semiconductor stack includes a lower semiconductor pattern structure filling a recess on a substrate and protruding from an upper surface of the substrate in a first direction substantially perpendicular to the upper surface of the substrate. The contact plug is disposed over the lower semiconductor patterns structure. The contact plug includes a lower portion and a middle portion over the lower portion. A width of the middle portion is less than a width of the lower portion. The gate electrodes are surrounding a sidewall of the semiconductor stack. The air gap structures are disposed at outer sides of the plurality of gate electrode respectively.