MEMS DEVICE AND PROCESS
    61.
    发明申请
    MEMS DEVICE AND PROCESS 审中-公开
    MEMS器件和工艺

    公开(公告)号:WO2014045042A1

    公开(公告)日:2014-03-27

    申请号:PCT/GB2013/052460

    申请日:2013-09-19

    Abstract: This application relates to MEMS devices, especially MEMS capacitive transducers and to processes for forming such MEMS transducer that provide increased robustness and resilience to acoustic shock. The application describes a MEMS transducer having a flexible membrane (101) supported relative to a first surface of a substrate (105) which has one or more cavities therein, e.g. to provide an acoustic volume. A stop structure (401, 402) is positioned so as to be contactable by the membrane when deflected so as to limit the amount of deflection of the membrane. The stop structure defines one or more openings to the one or more substrate cavities and comprises at least one narrow support element (401, 402) within or between said one or more openings. The stop structure thus limits the amount of membrane deflection, thus reducing the stress experienced at the edges and prevents the membrane from contacting a sharp edge of a substrate cavity. As the stop structure comprises narrow support elements any performance impact on the transducer is limited.

    Abstract translation: 本申请涉及MEMS器件,特别是MEMS电容式换能器,以及用于形成这样的MEMS换能器的方法,其提供对声学冲击的增强的鲁棒性和弹性。 该应用描述了一种MEMS传感器,其具有相对于其中具有一个或多个空腔的衬底(105)的第一表面支撑的柔性膜(101)。 以提供声音体积。 定位结构(401,402)被定位成当偏转时能够被膜接触,以限制膜的偏转量。 止挡结构限定了一个或多个开口到一个或多个基底空腔,并且包括在所述一个或多个开口之内或之间的至少一个窄支撑元件(401,402)。 因此,止挡结构限制了膜偏转的量,从而减小了边缘处的应力,并且防止了膜接触衬底腔的尖锐边缘。 由于止动结构包括窄支撑元件,所以对换能器的任何性能影响都受到限制。

    HEADPHONE DEVICE
    62.
    发明申请
    HEADPHONE DEVICE 审中-公开
    耳机设备

    公开(公告)号:WO2013011275A1

    公开(公告)日:2013-01-24

    申请号:PCT/GB2012/051590

    申请日:2012-07-06

    Inventor: NARAYAN, Renjish

    CPC classification number: H04R1/1083

    Abstract: A headphone comprises a speaker. The rear volume of the speaker is coupled to a mixing volume, the front volume of the speaker is coupled to the mixing volume, and the mixing volume is coupled to the exterior. The acoustic impedances resulting from the rear volume, the front volume, the mixing volume, and the passages between them can be adjusted, in order to achieve the desired sound egress properties. Acoustic damping material can be included in the various leakage paths in order to achieve the desired properties, depending on the type of speaker to be used, the acoustic design of the headphone, the mechanical properties of the headphone body, and the desired frequency response characteristics of the headphone.

    Abstract translation: 耳机包括扬声器。 扬声器的后部体积耦合到混合体积,扬声器的前部体积耦合到混合体积,并且混合体积耦合到外部。 可以调节从后体积,前体积,混合体积以及它们之间的通道产生的声阻抗,以便实现期望的声音出口性能。 根据所使用的扬声器的类型,耳机的声学设计,耳机的机械特性和期望的频率响应特性,声阻尼材料可以被包括在各种泄漏路径中以实现期望的性质 的耳机。

    CHARGE PUMP CIRCUIT
    63.
    发明申请
    CHARGE PUMP CIRCUIT 审中-公开
    电荷泵电路

    公开(公告)号:WO2012085598A2

    公开(公告)日:2012-06-28

    申请号:PCT/GB2011/052580

    申请日:2011-12-23

    Abstract: A bipolar output charge pump circuit 100 is provided having a network of switching paths 110 for selectively connecting an input node (VV) and a reference node (VG) for connection to an input voltage, a first pair of output nodes (VP, VN) and a second pair of output nodes (VQ, VM), and two pairs of flying capacitor nodes (CF1A, CF1B; CF2A, CF2B), and a controller for controlling the switching of the network of switching paths. The controller is operable to control the network of switching paths when in use with two flying capacitors (CF1, CF2) connected to the two pairs of flying capacitor nodes, to provide a first bipolar output voltage at the first pair of output nodes (VP, VN) and a second bipolar output voltage at the second pair of bipolar output nodes (VQ, VM).

    Abstract translation: 提供双极输出电荷泵电路100,其具有用于选择性地连接输入节点(VV)和参考节点(VG)以连接到输入电压的开关路径110的网络,第一对 的输出节点(VP,VN)和第二对输出节点(VQ,VM),以及两对快速电容器节点(CF1A,CF1B; CF2A,CF2B),以及控制器,用于控制切换网络 路径。 控制器可操作以在连接到两对飞电容器节点的两个飞跨电容器(CF1,CF2)使用时控制切换路径的网络,以在第一对输出节点(VP, VN)和第二对双极输出节点(VQ,VM)处的第二双极性输出电压。

    POWER MANAGEMENT APPARATUS AND METHODS
    65.
    发明申请

    公开(公告)号:WO2011010150A3

    公开(公告)日:2011-01-27

    申请号:PCT/GB2010/051198

    申请日:2010-07-21

    Abstract: This invention relates to apparatus and method for power management and especially to power management integrated circuits (PMICs). In one aspect the invention relates to a PMIC (102) having an internal non-volatile memory (NVM 115) for storing boot settings for the PMIC. The PMIC also has control circuitry (111) for detecting whether a source of boot settings is available, such as an NVM (202) external to the PMIC, and, if so, using any settings stored in the external source in preference to the relevant settings stored in the internal NVM. The external settings can thus override any internal settings, which is useful for fault diagnosis and/or development. In one aspect the PMIC may have programming circuitry (401) for automatically programming boot settings from an external source into the internal NVM (115).

    INTEGRATED CIRCUIT PACKAGE
    66.
    发明申请
    INTEGRATED CIRCUIT PACKAGE 审中-公开
    集成电路封装

    公开(公告)号:WO2011010149A1

    公开(公告)日:2011-01-27

    申请号:PCT/GB2010/051197

    申请日:2010-07-21

    CPC classification number: G06F12/0223 H01L25/0657 H01L2924/0002 H01L2924/00

    Abstract: The present invention provides an integrated circuit combination (18), comprising first and second integrated circuit dies (19, 20) with respective first and second control register banks (28, 36), and a path for external control data, within said combination, coupling a first data interface (24) on said first die, which receives the external control data, to the first and second control register banks.

    Abstract translation: 本发明提供一种集成电路组合(18),包括具有相应的第一和第二控制寄存器组(28,36)的第一和第二集成电路管芯(19,20),以及在所述组合内的用于外部控制数据的路径, 将接收外部控制数据的所述第一管芯上的第一数据接口(24)耦合到第一和第二控制寄存器组。

    IMPROVEMENTS RELATING TO DC-DC CONVERTERS
    67.
    发明申请
    IMPROVEMENTS RELATING TO DC-DC CONVERTERS 审中-公开
    与DC-DC转换器相关的改进

    公开(公告)号:WO2011010143A2

    公开(公告)日:2011-01-27

    申请号:PCT/GB2010/051190

    申请日:2010-07-20

    Abstract: This invention relates to methods and apparatus for control of DC-DC converters, especially in valley current mode. The DC-DC converter (100) is operable so that a low side supply switch (20) may be turned off, before the high side supply switch (10) is turned on. During the period when both switches are off the current loop control (501) remains active and the change in inductor (L) current is emulated. One embodiment uses a current sensor (800) for lossless current sensing and emulates the change in inductor current by holding the value of the output of the current sensor (ISNS) at the time that the low side switch turns off and adding an emulated ramp signal (VISLP) until the inductor current reaches zero. Embodiment employing a pulse-skip mode of operation based on a minimum conduction time are also disclosed. The invention enables a seamless transition from Continuous Conduction Mode the Discontinuous Conduction Mode and Pulse Skipping and provide converters that are efficient at low current loads.

    Abstract translation: 本发明涉及用于控制DC-DC转换器的方法和装置,特别是在谷电流模式下。 在高侧供电开关(10)接通之前,DC-DC转换器(100)可操作使得可以关断低侧供电开关(20)。 在两个开关断开期间,电流环路控制(501)保持有效,并且仿真电感(L)电流的变化。 一个实施例使用电流传感器(800)进行无损耗电流检测,并且通过在低侧开关断开时保持电流传感器(ISNS)的输出值并且添加仿真斜坡信号来模拟电感器电流的变化 (VISLP),直到电感电流达到零。 还公开了采用基于最小导通时间的脉冲跳过操作模式的实施例。 本发明实现了从连续导通模式不连续导通模式和脉冲跳跃的无缝转换,并提供了在低电流负载下有效的转换器。

    LEVEL-SHIFTER CIRCUIT
    68.
    发明申请
    LEVEL-SHIFTER CIRCUIT 审中-公开
    LEVEL-SHIFTER电路

    公开(公告)号:WO2011010142A2

    公开(公告)日:2011-01-27

    申请号:PCT/GB2010051189

    申请日:2010-07-20

    Abstract: There is provided a level-shift circuit, comprising: an input, for receiving a first voltage; an output, for outputting a second voltage; a resistor array comprising one or more resistors connected in series to the input; a current sink for providing a current that is independent of the first voltage; a switch arrangement comprising a plurality of switch connections for establishing a selected one from a plurality of force paths between the current sink and the input, said selected force path comprising a selected number of said one or more resistors of said resistor array; and at least one connection between the output and the resistor array that provides a sense path between the resistor array and the output that does not comprise any of said switch connections used to establish each of said plurality of force paths.

    Abstract translation: 提供了一种电平转换电路,包括:输入端,用于接收第一电压; 输出端,用于输出第二电压; 包括串联连接到所述输入的一个或多个电阻器的电阻器阵列; 用于提供独立于所述第一电压的电流的电流吸收器; 开关装置,包括多个开关连接,用于建立从所述电流吸收器和所述输入之间的多个力路径中选择的一个,所述选择的力路径包括所述电阻器阵列的选定数量的所述一个或多个电阻器; 以及输出端和电阻器阵列之间的至少一个连接端,其在电阻器阵列和输出端之间提供感测路径,所述感测路径不包括用于建立所述多个力路径中的每一个的所述开关连接中的任何一个。

    IMPROVEMENTS IN DC-DC CONVERTERS
    69.
    发明申请
    IMPROVEMENTS IN DC-DC CONVERTERS 审中-公开
    DC-DC转换器的改进

    公开(公告)号:WO2011010141A2

    公开(公告)日:2011-01-27

    申请号:PCT/GB2010/051188

    申请日:2010-07-20

    Abstract: This invention relates to apparatus and method for providing current limiting in a DC- DC converter and especially to methods and apparatus suitable for a start-up mode of operation. The invention monitors the inductor (L) current when the high side supply switch (10) is on against a peak current limit threshold (5001). If the inductor current reaches the peak current limit threshold the high side switch is turned off. The inductor current when the low side switch is off is monitored against a valley current threshold (5002). As long as the inductor current is above the valley current threshold turn on of the low side switch is inhibited. In this way current limiting is provided and the problems of stair-stepping are avoided. Embodiments employing lossless current sensing are described. The invention may be implemented in a start-up mode of operation wherein the converter is controlled purely by the peak current limit and valley current threshold which are increased over time.

    Abstract translation: 本发明涉及用于在DC-DC转换器中提供电流限制的设备和方法,并且尤其涉及适用于启动操作模式的方法和设备。 本发明在高侧供电开关(10)接通时针对峰值电流极限阈值(5001)监测电感器(L)电流。 如果电感电流达到峰值限流门限,高端开关将关闭。 针对谷值电流阈值(5002)监测低侧开关断开时的电感器电流。 只要电感电流高于谷值电流阈值,低端开关的导通就被禁止。 通过这种方式提供了电流限制,避免了阶梯式步进的问题。 描述采用无损电流感测的实施例。 本发明可以在启动操作模式中实现,其中转换器完全由随着时间增加而增加的峰值电流限制和谷值电流阈值来控制。

    REAL TIME CLOCK
    70.
    发明申请
    REAL TIME CLOCK 审中-公开
    实时时钟

    公开(公告)号:WO2009101445A1

    公开(公告)日:2009-08-20

    申请号:PCT/GB2009/050142

    申请日:2009-02-13

    CPC classification number: G06F21/725

    Abstract: A real time clock apparatus (20) comprises a counter (23) which stores a count value, the count value representing a time signal. The counter (23) may be written, for example by a host processor (not shown), such that the time signal can be set to any desired value. The real time clock apparatus (20) comprises a check register (33) that stores a check value. The content of the check register (33) (i.e. the check value) is modified each time a write operation is performed on the counter (23). For example, the content of the check register (33) can be updated by a control signal (35) each time a write operation is performed on the counter (23). The check value stored in the check register (33) is used for determining whether a write operation performed on the counter (23) is an authorised write operation or an unauthorised write operation. The check value may be incremented each time a write operation is performed, replaced with a new random number each time a write operation is performed, or a combination of both.

    Abstract translation: 实时时钟装置(20)包括存储计数值的计数器(23),计数值表示时间信号。 计数器(23)可以例如由主处理器(未示出)写入,使得时间信号可以被设置为任何期望值。 实时时钟装置(20)包括存储检查值的检查寄存器(33)。 每当对计数器(23)执行写入操作时,校验寄存器(33)的内容(即校验值)被修改。 例如,每当在计数器(23)上执行写入操作时,可以通过控制信号(35)更新检查寄存器(33)的内容。 存储在检查寄存器(33)中的检查值用于确定对计数器(23)执行的写入操作是否是授权写入操作或未经授权的写入操作。 每次执行写入操作时,可以增加检查值,每当执行写入操作时,用新的随机数替换检查值,或者两者的组合。

Patent Agency Ranking