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公开(公告)号：KR1020090039094A
公开(公告)日：2009-04-22
申请号：KR1020070104534
申请日：2007-10-17
Applicant: 삼성전기주식회사
CPC classification number: H01L2224/24227 , H01L2924/15153 , H01L2924/1517 , H01L24/10 , H01L23/31 , H01L23/3735 , H01L23/481 , H01L23/522
Abstract: A semiconductor package and a manufacturing method thereof are provided to reduce the number of build up layers by excluding a conductive bump for protecting an electrode of a semiconductor chip. A manufacturing method of a semiconductor package comprises the following steps: a step for providing a semiconductor chip on which a molding frame and a protective layer are formed(S100); a step for laminating a fixing film on one surface of the molding frame(S110); a step for inserting the semiconductor chip in a through hole of the molding frame(S120); a step for fixing the semiconductor chip to the molding frame by filling insulation material between the semiconductor chip and the molding frame(S130); a step for forming a radiation plate on the other surface of the molding frame in order to cover the other surface of the semiconductor chip(S140); a step for removing the fixing film(S150); a step for forming a first via on the protective layer in order to be connected to an electrode(S160); a step for forming a build up layer on one surface of the molding frame in order to cover one surface of the semiconductor chip(S170); a step for forming a second via connected to the first via on the build up layer(S180); and a step for forming a bump connected to the second via on one surface of the build up layer(S190).
Abstract translation: 提供半导体封装及其制造方法，通过排除用于保护半导体芯片的电极的导电凸块来减少堆积层的数量。 半导体封装的制造方法包括以下步骤：提供形成有模制框架和保护层的半导体芯片的步骤（S100）; 用于在所述模制框架的一个表面上层压定影膜的步骤（S110）; 将半导体芯片插入模制框架的通孔中的步骤（S120）; 通过在半导体芯片和模制框架之间填充绝缘材料将半导体芯片固定到模制框架的步骤（S130）; 在所述模制框架的另一表面上形成辐射板以覆盖所述半导体芯片的另一个表面的步骤（S140）; 去除定影膜的步骤（S150）; 在保护层上形成第一通孔以便连接到电极的步骤（S160）; 在模制框架的一个表面上形成堆积层以覆盖半导体芯片的一个表面的步骤（S170）; 用于形成连接到建立层上的第一通孔的第二通路的步骤（S180）; 以及在构成层的一个表面上形成连接到第二通孔的凸块的步骤（S190）。
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公开(公告)号：KR1020090002887A
公开(公告)日：2009-01-09
申请号：KR1020070067253
申请日：2007-07-04
Applicant: 삼성전기주식회사
IPC: H01L23/12
CPC classification number: H01L21/78 , H01L21/0231 , H01L21/0273 , H01L21/268 , H01L23/481 , H01L23/4828
Abstract: The wafer level device packaging method is provided to prevent the generation of warpage in the thermal process and to reduce the stress about the wafer for device substrate and the wafer for the cap substrate. The wafer(10) for the cap substrate is mounted on the wafer supporter (Wafer Support Substrate)(20) by the medium of the adhesive(12). The separate space(13) is formed for setting up the cutting line(50) and for surrounding a plurality of vias(11). The upper seal ring pattern(14) is formed with the closed line. The wafer supporter and the wafer are bonded by adhesive. The warpage by the thermal expansion can be prevented by the separate space.
Abstract translation: 提供了晶片级装置封装方法以防止在热处理中产生翘曲并且减小用于器件衬底的晶片和盖衬底的晶片的应力。 用于盖基板的晶片（10）通过粘合剂（12）的介质安装在晶片支撑件（晶片支撑基板）（20）上。 分离空间（13）形成用于设置切割线（50）并围绕多个通路（11）。 上密封圈图案（14）形成有闭合线。 晶片支架和晶片通过粘合剂粘合。 可以通过分开的空间来防止热膨胀的翘曲。
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公开(公告)号：KR100870864B1
公开(公告)日：2008-11-28
申请号：KR1020070099228
申请日：2007-10-02
Applicant: 삼성전기주식회사
CPC classification number: H01L23/3114 , H01L21/6835 , H01L24/11 , H01L24/12 , H01L24/24 , H01L24/27 , H01L24/82 , H01L2221/68372 , H01L2224/0231 , H01L2224/0401 , H01L2224/16 , H01L2224/24227 , H01L2224/274 , H01L2924/01006 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01059 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/15153 , H01L2924/1517
Abstract: The increase of the manufacturing cost due to the re-ordering layer formed by the semiconductor process can be prevented. The wafer level package production method is provided. A step(S10) is for penetrating the substrate to form a cavity. A step(S20) is for attaching the bonding layer in one side of substrate(S20). A step(S40) is for settling the wafer substrate in one side of the bonding layer by inserting the wafer substrate into the cavity. A step(S51) is for laminating the insulating layer in the wafer substrate. A step(S52) is for processing the via hole in the insulating layer. A step(S53) is for forming the seed layer in the insulating layer. A step(S54) is for forming the plating resist corresponding to the rearranging pattern in the seed layer. A step(S55) is for forming the rearranging pattern including the terminal for the external connectivity through electroplating. A step(S110) is for uniting the conductive ball in the terminal.
Abstract translation: 可以防止由于通过半导体工艺形成的再排序层引起的制造成本的增加。 提供了晶片级封装生产方法。 步骤（S10）用于穿透基板以形成空腔。 步骤（S20）用于在基板的一侧安装接合层（S20）。 步骤（S40）用于通过将晶片衬底插入空腔中来将晶片衬底沉积在接合层的一侧。 步骤（S51）用于在晶片衬底中层叠绝缘层。 步骤（S52）用于处理绝缘层中的通孔。 步骤（S53）用于在绝缘层中形成种子层。 步骤（S54）用于形成与种子层中的重排图案相对应的电镀抗蚀剂。 步骤（S55）用于通过电镀形成包括用于外部连接的端子的重排图案。 步骤（S110）用于将导电球结合在端子中。
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公开(公告)号：KR100866619B1
公开(公告)日：2008-11-03
申请号：KR1020070097803
申请日：2007-09-28
Applicant: 삼성전기주식회사
IPC: H01L23/12 , H01L27/146
CPC classification number: H01L27/14618 , H01L27/14683 , H01L2224/02372 , H01L2224/05001 , H01L2224/05009 , H01L2224/05024 , H01L2224/05548 , H01L2224/13 , H01L2924/00014 , H01L2224/05599
Abstract: An interconnection process for the external connection including via etc can be facilitated. The reliability can be improved. The focusing unregulated can be achieved in using a camera module. The image sensor includes a wafer(11); the image sensor(12) mounted on the wafer; the transparent member mounted on the wafer in order to seal the image sensor; the via which is formed on wafer and located in the outer side of the transparent member(14); the upper pad(15) formed in the top end portion of via; the encapsulation part(16) formed in the outer side of the transparent member in the upper side of wafer; the external connection member(18) electrically connected to the bottom part of via.
Abstract translation: 可以促进用于包括通孔等的外部连接的互连处理。 可靠性得到提高。 在使用相机模块时可以实现未调节的对焦。 图像传感器包括晶片（11）; 安装在晶片上的图像传感器（12） 透明构件安装在晶片上以便密封图像传感器; 形成在晶片上并位于透明构件（14）的外侧的通孔; 上焊盘（15）形成在通孔的顶端部分中; 形成在晶片上侧的透明构件的外侧的封装部（16） 电连接到通孔的底部的外部连接构件（18）。
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Patent Agency Ranking
公开(公告)号：KR102172632B1
公开(公告)日：2020-11-03
申请号：KR20150092903
申请日：2015-06-30
Applicant: 삼성전기주식회사
Abstract: 본발명의일 실시예에따른반도체패키지모듈제조장치는하나이상의소자가실장된기판이안착되는하부금형, 상기기판을수용한상태로상기기판의상측에구비되는상부금형, 상기상부금형또는상기하부금형중 적어도하나에구비되며, 상기기판과상기상부금형사이에몰딩부를형성하도록충진재를공급하는몰딩수단및 상기기판과대면하는상기상부금형의내부면에구비되어요철형상을제공하는패턴형성수단을포함할수 있다. 또한, 본발명의다른실시예에따른반도체패키지모듈제조방법은하나이상의소자가실장된기판에충진재를공급후에경화시켜몰딩부를형성하며, 상기몰딩부의경화중에상기몰딩부외부면의표면조도를높이도록요철형상을형성하는것을특징으로할 수있다.
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公开(公告)号：KR1020170111913A
公开(公告)日：2017-10-12
申请号：KR1020160038205
申请日：2016-03-30
Applicant: 삼성전기주식회사
CPC classification number: H03H3/02 , H03H3/08 , H03H9/1014 , H03H9/1071
Abstract: 본발명의일 실시예에따른음향파디바이스는일면에음향파발생부와적어도하나의접지패드가구비된기판, 상기기판의일면에상기음향파발생부와이격되게구비되는지지부, 상기지지부상에적층되며상기음향파발생부와이격배치되는차폐부재, 및상기접지패드상에배치되는접지단자를포함하며, 상기접지패드와상기차폐부재는상기접지단자를통해서로전기적으로연결될수 있다.
Abstract translation: 在根据本发明的一个实施例的弹性波装置是，所提供的至少一个接地焊盘和表面基材上的声音韦帕生物父亲，对设置成从声学韦帕生物父亲隔开在基板的一个表面上层叠在支撑部的一部分 以及设置在所述声韦帕生物父亲具有间隔屏蔽部件的接地端子，和地面垫，所述接地焊盘和所述屏蔽构件可电通过接地端子相连接英寸
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公开(公告)号：KR1020170032149A
公开(公告)日：2017-03-22
申请号：KR1020160031352
申请日：2016-03-16
Applicant: 삼성전기주식회사
Abstract: 본발명의일 실시예에따른음향파디바이스는일면에음향파발생부와적어도하나의접지패드를구비하는기판, 절연성재질로형성되고상기음향파발생부의둘레를따라상기기판에배치되는지지부, 및상기접지패드와전기적으로연결되며상기음향파발생부에전자기파가유입되거나유출되는것을차폐하는차폐부재를포함할수 있다.
Abstract translation: 在根据本发明的一个实施例的声波器件的基板，形成具有至少一个接地焊盘和在一个表面上的声韦帕生物父亲沿着设置在所述衬底中的所述声波发生器单元部分的周边，并且其中，由绝缘材料 以及屏蔽构件，其电连接到接地垫并且屏蔽电磁波进入或离开声波断路器。
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公开(公告)号：KR1020160010640A
公开(公告)日：2016-01-27
申请号：KR1020160004084
申请日：2016-01-13
Applicant: 삼성전기주식회사
Abstract: 공통모드필터및 그제조방법을개시한다. 공통모드필터는기판, 기판상에배치되어신호노이즈를제거하는필터층, 내측모서리부분이곡면으로형성되며필터층과전기적으로연결되는복수의외부전극, 및필터층상에서복수의외부전극사이를충진하여형성된자성층을포함한다.
Abstract translation: 公开了共模滤波器及其制造方法。 共模滤波器包括：基板; 布置在基板上以消除信号噪声的滤波层; 多个外部电极，其内边缘部分形成为弯曲，其中外部电极电连接到过滤层; 以及通过填充过滤层上的多个外部电极之间的间隙而形成的磁性层。
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公开(公告)号：KR101530066B1
公开(公告)日：2015-06-18
申请号：KR1020140059857
申请日：2014-05-19
Applicant: 삼성전기주식회사
CPC classification number: H03H7/427 , H01F17/0013 , H01F27/245 , H01F27/2804 , H01F41/0206 , H01F41/041 , H01F41/046 , H01F2017/0066 , H01F2017/0093 , H03H3/013 , H03H7/17 , H03H2001/0057 , H03H2001/0085 , Y10T156/10 , H01F17/00
Abstract: 공통모드필터및 그제조방법이개시된다. 본발명의일 측면에따른공통모드필터는기판, 코일및 절연층을포함하고, 기판상에배치되어신호노이즈를제거하는필터층및 필터층에적층되는자성층을포함하고, 필터층은자성층과접합되는면에코일의일면이노출되도록코일이매립되어자성층과접합되는면이평탄하게형성된다.
Abstract translation: 公开了共模滤波器及其制造方法。 根据本发明的一个方面的共模滤波器包括基板，线圈和绝缘层，形成在基板上并去除单个噪声的滤波层以及层叠在滤波层上的磁性层。 线圈被埋在滤光层中，以暴露在接触磁性层的表面上的线圈的一侧。 因此，接触磁性层的表面变得平坦。
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