公开(公告)号：KR1020150061973A

公开(公告)日：2015-06-05

申请号：KR1020130146405

申请日：2013-11-28

Applicant: 삼성전기주식회사

Inventor： 장창수 ,  송인혁 ,  박재훈 ,  서동수

IPC: H01L29/739 ,  H01L29/78 ,  H01L21/331 ,  H01L21/336

CPC classification number: H01L29/73 ,  H01L29/0615 ,  H01L29/0878 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813

Abstract: 본발명은온-동작시에형성되는채널을통해전류가흐르는활성영역; 상기활성영역의주변에형성되는단부영역; 상기활성영역에형성되며, 일방향으로길게형성되는복수의트랜치; 상기활성영역에형성되며, 상기채널의하부에형성되는제1 도전형의정공축적영역; 및상기단부영역에형성되는제1 도전형의전계제한영역;을포함하고, 상기전계제한영역은상기활성영역과상기단부영역의경계에위치하는상기트랜치의적어도일부를덮도록형성되는전력반도체소자에관한것이다.

Abstract translation: 本发明涉及一种功率半导体器件，其包括有源区，其中形成在工作区中的电流流过形成在有源区周围的端部区域，多个沟槽形成在有源区上 并且在一个方向上形成长;形成在有源区上并形成在沟道的下侧的第一导电型空穴积聚区和形成在端部区域上的第一导电型电场限制区 。 电场限制区域覆盖位于有源区域和端部区域之间的边界中的沟槽的至少一部分。

公开(公告)号：KR1020150018267A

公开(公告)日：2015-02-23

申请号：KR1020130094957

申请日：2013-08-09

Applicant: 삼성전기주식회사

Inventor： 송인혁 ,  박재훈 ,  엄기주 ,  서동수

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/739

CPC classification number: H01L29/063 ,  H01L29/0611 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/1095 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/4916 ,  H01L29/43 ,  H01L29/66325 ,  H01L29/7393 ,  H01L29/772

Abstract: 본 발명은 제1 도전형의 제1 드리프트 층; 상기 드리프트 층의 두께 방향의 상부에 형성되며, 폭 방향으로 제1 도전형의 제1 반도체 영역과 제2 도전형의 제2 반도체 영역이 교번하여 형성되는 제1 내지 n 리써프 층; 상기 제n 리써프 층의 두께 방향의 상부에 형성되는 제1 도전형의 제2 드리프트 층; 상기 제2 드리프트 층에 형성되며, 상기 제2 반도체 영역의 상부에 형성되는 제2 도전형의 웰 영역; 상기 웰 영역의 상부에 형성되는 제1 도전형의 소스 영역;을 포함하고, 상기 제1 내지 n 리써프 층에 형성되는 상기 제2 반도체 영역의 폭 방향으로 가장 긴 부분의 길이를 P이라고 할 때, P
n
-1 n (단, n≥2)인 전력 반도체 소자에 관한 것이다.

Abstract translation: 本发明涉及一种功率半导体器件，其包括第一导电类型的第一漂移层，形成在漂移层的厚度方向的上侧上的第一至第n复层，并且通过交替地布置 第一导电类型的第一半导体区域和宽度方向上的第二导电类型的第二半导体区域，第一导电类型的第二漂移层形成在第n导电类型的第n导电类型的厚度方向的上侧上 形成在第二漂移层和第二半导体区域的上侧的第二导电类型的阱区，以及形成在阱区的上侧的第一导电类型的源极区域。 当形成在第1〜第n层上的第2半导体区域的宽度方向的最长长度为P时，满足Pn-1 = 2）。

公开(公告)号：KR1020140077601A

公开(公告)日：2014-06-24

申请号：KR1020120146587

申请日：2012-12-14

Applicant: 삼성전기주식회사

Inventor： 엄기주 ,  송인혁 ,  장창수 ,  박재훈 ,  서동수

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7397 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66348

Abstract: The present invention relates to a power semiconductor device. The power semiconductor device includes a contact which is formed on an active region; a trench gate which is extended from the active region to a first end region and is formed alternately with the contact; a first conductivity type well which is formed between the contact part and the trench gate of the active region; a first conductivity type well extension part which is formed on a portion of the first end region and a second end region; and a first conductivity type field limiting ring which is in contact with the well extension part.

Abstract translation: 功率半导体器件技术领域本发明涉及功率半导体器件。 功率半导体器件包括形成在有源区上的触点; 沟槽栅极，其从有源区域延伸到第一端部区域，并且与接触件交替地形成; 形成在有源区的接触部和沟槽栅之间的第一导电型阱; 形成在第一端部区域的一部分上的第一导电型阱延伸部和第二端区; 以及与阱延伸部分接触的第一导电型场限制环。

公开(公告)号：KR1020140076762A

公开(公告)日：2014-06-23

申请号：KR1020120145167

申请日：2012-12-13

Applicant: 삼성전기주식회사

Inventor： 김광수 ,  서범석 ,  정인화 ,  박지현 ,  박재훈

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/78 ,  H01L29/0653 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/66568 ,  H01L29/7827 ,  H01L29/41725 ,  H01L29/0886

Abstract: The present invention relates to a power semiconductor device and a method for manufacturing the same. The power semiconductor device according to one embodiment of the present invention includes a first conductivity type body region; a second conductivity type wall which is formed in the upper part of the body region; and a conductive via which crosses the wall and is formed in the body region. According to one embodiment of the present invention, the conductive via penetrates the body region.

Abstract translation: 功率半导体器件及其制造方法技术领域本发明涉及功率半导体器件及其制造方法。 根据本发明的一个实施例的功率半导体器件包括第一导电类型的主体区域; 第二导电型壁，其形成在所述身体区域的上部; 以及穿过所述壁并形成在所述身体区域中的导电通路。 根据本发明的一个实施例，导电通孔穿透身体区域。

公开(公告)号：KR1020140074027A

公开(公告)日：2014-06-17

申请号：KR1020120142172

申请日：2012-12-07

Applicant: 삼성전기주식회사

Inventor： 엄기주 ,  송인혁 ,  장창수 ,  박재훈 ,  서동수

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7397 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/66348

Abstract: The power semiconductor device according to the present invention includes: a first conductive type semiconductor substrate which has one side and the other side; a second conductive type drift layer which is formed on the one side of the semiconductor substrate; a second conductive type well layer which is formed on the drift layer; a trench which is formed to reach the drift layer by penetrating the well layer in a thickness direction; a first electrode which is formed in the trench; a second electrode area which is selectively formed on the well layer, is formed with the first area which perpendicularly touches the trench and a second area which is perpendicular to the first area by being separated from the trench in parallel, and has a concentration which is higher than the drift layer; a first conductive type second electrode area which is formed to be in contact with the lateral side of a second conductive type second electrode area on the well layer and has a concentration which is higher than the well layer; and a second electrode which is electrically connected with the second conductive type second electrode area and the first conductive type second electrode area by being formed on the well layer.

Abstract translation: 根据本发明的功率半导体器件包括：具有一侧和另一侧的第一导电型半导体衬底; 第二导电型漂移层，其形成在所述半导体衬底的一侧上; 形成在漂移层上的第二导电类型阱层; 形成为通过沿厚度方向穿透阱层而到达漂移层的沟槽; 形成在沟槽中的第一电极; 选择性地形成在阱层上的第二电极区域形成有与沟槽垂直接触的第一区域和与沟槽平行分离的与第一区域垂直的第二区域，其浓度为 高于漂移层; 第一导电类型的第二电极区域，其形成为与阱层上的第二导电类型的第二电极区域的侧面接触并且具有高于阱层的浓度; 以及通过形成在所述阱层上而与所述第二导电型第二电极区域和所述第一导电型第二电极区域电连接的第二电极。

公开(公告)号：KR1020140073325A

公开(公告)日：2014-06-16

申请号：KR1020120141454

申请日：2012-12-06

Applicant: 삼성전기주식회사

Inventor： 엄기주 ,  서동수 ,  장창수 ,  송인혁 ,  박재훈

IPC: H01L29/739 ,  H01L29/78 ,  H01L21/331

CPC classification number: H01L29/7395 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/404 ,  H01L29/423 ,  H01L29/66333

Abstract: The present invention relates to a power semiconductor device and a method for manufacturing the same. The power semiconductor device according to one embodiment of the present invention includes a first conductivity type drift layer; a second conductivity type end layer which is formed in the upper part of the drift layer; and a first conductivity type channel stop layer of high concentration which is formed in the end part of the drift layer. According to one embodiment of the present invention, the depth of the channel stop layer is greater than that of the end layer.

Abstract translation: 功率半导体器件及其制造方法技术领域本发明涉及功率半导体器件及其制造方法。 根据本发明的一个实施例的功率半导体器件包括第一导电型漂移层; 第二导电型端层，形成在漂移层的上部; 以及形成在漂移层的端部的高浓度的第一导电型沟道阻挡层。 根据本发明的一个实施例，通道阻挡层的深度大于端层的深度。

公开(公告)号：KR1020140067445A

公开(公告)日：2014-06-05

申请号：KR1020120134700

申请日：2012-11-26

Applicant: 삼성전기주식회사

Inventor： 송인혁 ,  엄기주 ,  장창수 ,  박재훈 ,  서동수

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/402 ,  H01L29/0619 ,  H01L29/41741 ,  H01L29/66348 ,  H01L29/7397

Abstract: A power semiconductor device according to an embodiment of the present invention comprises: a second conductive type first junction termination extension (JTE) layer formed to be in contact with one side of a second conductive type well layer; a second conductive type second JTE layer formed on a same line of the second conductive type first JTE layer and to be spaced apart from the second conductive type first JTE layer in the longitudinal direction of a substrate; and a poly silicon layer formed to be in contact with the second conductive type well layer and the second conductive type first JTE layer.

Abstract translation: 根据本发明的实施例的功率半导体器件包括：形成为与第二导电类型阱层的一侧接触的第二导电型第一接合端接延伸（JTE）层; 第二导电类型的第二JTE层，形成在第二导电型第一JTE层的同一线上，并且在基板的纵向方向上与第二导电型第一JTE层间隔开; 以及形成为与第二导电类型阱层和第二导电型第一JTE层接触的多晶硅层。

公开(公告)号：KR101388706B1

公开(公告)日：2014-04-24

申请号：KR1020120095649

申请日：2012-08-30

Applicant: 삼성전기주식회사

Inventor： 송인혁 ,  박재훈 ,  서동수

IPC: H01L21/336 ,  H01L29/70

CPC classification number: H01L29/6634 ,  H01L21/046 ,  H01L21/22 ,  H01L21/2253 ,  H01L21/265 ,  H01L21/3081 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/4236 ,  H01L29/66325 ,  H01L29/66348 ,  H01L29/66674 ,  H01L29/7393 ,  H01L29/7397 ,  H01L29/7825

Abstract: 본 발명의 실시예는 전력 반도체 소자 및 그 제조방법에 관한 것으로서, 일면 및 타면을 갖고, 제1 도전형 드리프트(Drift)층으로 형성된 베이스기판; 베이스기판의 일면에 형성되되, 제1 도전형 드리프트층 보다 고농도의 제1 도전형 확산층; 제2 도전형 웰층을 포함하여 베이스기판의 일면으로부터 제2 도전형 웰층 및 제1 도전형 확산층을 두께 방향으로 관통하도록 형성된 트렌치;를 포함하는 것을 특징으로 한다.

公开(公告)号：KR101339574B1

公开(公告)日：2013-12-10

申请号：KR1020120095846

申请日：2012-08-30

Applicant: 삼성전기주식회사

Inventor： 송인혁 ,  박재훈 ,  서동수

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/41708 ,  H01L29/0821 ,  H01L29/0834 ,  H01L29/66325 ,  H01L29/7397

Abstract: The present invention relates to an insulated gate bipolar transistor. The insulated gate bipolar transistor includes an active region including a gate electrode, a first emitter metal, a first well region and a part of a third well region; an end region including a second wall region supporting the extension of a depletion layer; a connection region including a second emitter metal, a gate metal, and a part of the third well region and located between the active region and the end region. The third region is formed in the active region and the connection region. The first emitter metal and the second emitter metal is formed in the upper part of the third wall region.

Abstract translation: 本发明涉及绝缘栅双极晶体管。 绝缘栅双极晶体管包括有源区，包括栅电极，第一发射极金属，第一阱区和第三阱区的一部分; 包括支撑耗尽层的延伸的第二壁区域的端部区域; 包括第二发射极金属，栅极金属和第三阱区的一部分并且位于有源区和端区之间的连接区。 第三区域形成在有源区域和连接区域中。 第一发射极金属和第二发射极金属形成在第三壁区域的上部。

公开(公告)号：KR101301414B1

公开(公告)日：2013-08-28

申请号：KR1020120077332

申请日：2012-07-16

Applicant: 삼성전기주식회사

Inventor： 김광수 ,  서범석 ,  송인혁 ,  박재훈 ,  서동수

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7813 ,  H01L29/045 ,  H01L29/0623 ,  H01L29/4236 ,  H01L29/518 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7395 ,  H01L29/7397

Abstract: PURPOSE: A semiconductor device and a method for manufacturing the semiconductor device are provided to minimize the charge traps by forming a gate trench having clear inner walls. CONSTITUTION: An emitter region (170) is formed within a base region. The emitter region is formed at both sides of a gate electrode. An emitter metal layer (180) is formed on the upper part of the base region and the upper part of an interlayer dielectric. A buffer region (120) surrounds the lower part of the gate electrode. The buffer region is separated from the base region.

Abstract translation: 目的：提供一种用于制造半导体器件的半导体器件和方法，用于通过形成具有透明内壁的栅极沟槽来最小化电荷陷阱。 构成：在基极区域内形成发射极区域（170）。 发射极区域形成在栅电极的两侧。 发射极金属层（180）形成在基极区域的上部和层间电介质的上部。 缓冲区域（120）围绕栅电极的下部。 缓冲区域与基区域分离。