저전력 주파수 발생 회로
    61.
    发明公开
    저전력 주파수 발생 회로 无效
    低功率频率发生电路

    公开(公告)号:KR1020080112605A

    公开(公告)日:2008-12-26

    申请号:KR1020070061200

    申请日:2007-06-21

    Abstract: A low power frequency generating circuit including voltage control oscillator and frequency multiplier is provided to reduce a current consumption by simplifying a voltage source by a current reused mode. A low power frequency generating circuit includes a voltage control oscillator(21) and a frequency multiplier(22). The voltage control oscillator generates a frequency signal of a fixed range. The frequency multiplier receives the frequency signal generated in the voltage control oscillator, and outputs a frequency signal of an integral number multiple. The voltage control oscillator and the frequency multiplier are serially connected between a powered terminal and a ground terminal, and form a transmission path of a power current connected from the powered terminal to the ground terminal.

    Abstract translation: 提供包括电压控制振荡器和倍频器的低功率频率发生电路,以通过当前重用模式简化电压源来减少电流消耗。 低功率频率发生电路包括电压控制振荡器(21)和倍频器(22)。 电压控制振荡器产生固定范围的频率信号。 倍频器接收在压控振荡器中产生的频率信号,并输出整数倍数的频率信号。 电压控制振荡器和倍频器串联连接在电源端子和接地端子之间,并形成从供电端子连接到接地端子的电力电流的传输路径。

    수신기능을 갖는 폴러 송신 장치
    62.
    发明授权
    수신기능을 갖는 폴러 송신 장치 有权
    具有接收功能的极性发射器

    公开(公告)号:KR100826377B1

    公开(公告)日:2008-05-06

    申请号:KR1020070052091

    申请日:2007-05-29

    Inventor: 임준형 박타준

    CPC classification number: H04B1/0483 H04B1/0057 H04B1/0475

    Abstract: A polar transmitter having a receiving function is provided to check a BER(Bit Error Rate) by using a receiver while a separate external BER measurer is unnecessary, and to calibrate amplitude and a phase for an optimal BER. A multimode baseband circuit unit(100) converts I(In-phase)/Q(Quadrature-phase) signals into amplitude and phase signals, and calibrates the amplitude and phase signals according to calibrated amplitude/phase and a BER of output signals in accordance with I/Q signals provided in calibration mode. A DA(Digital to Analog) converter(300) converts a digital amplitude signal into an analog amplitude voltage. A phase modulator(600) modulates a phase signal into an RF(Radio Frequency) signal for transmission. A power amplifier(700) amplifies the RF signal by determining a gain according to the amplitude voltage. A path selector(800) switches on a normal mode path as switching off a calibration mode path connected to the normal mode path in parallel in case of a communication mode, and switches off the normal mode path as switching on the calibration mode path in case of a calibration mode. A receiver(900) restores output signals incoming through the path selector into I/Q signals to provide the restored signals to the baseband circuit unit.

    Abstract translation: 提供具有接收功能的极性发射机,通过使用接收机来检查BER(误码率),同时不需要单独的外部BER测量器,并校准幅度和相位以达到最佳BER。 多模基带电路单元(100)将I(同相)/ Q(正交)信号转换成幅度和相位信号,并且根据校准的幅度/相位和输出信号的BER来校准幅度和相位信号 在校准模式下提供I / Q信号。 DA(数模)转换器(300)将数字幅度信号转换成模拟幅度电压。 相位调制器(600)将相位信号调制成RF(射频)信号用于传输。 功率放大器(700)通过根据幅度电压确定增益来放大RF信号。 路径选择器(800)在通信模式的情况下,通过并联连接到通常模式路径的校准模式路径来切换正常模式路径,并且在打开校准模式路径时关闭正常模式路径 的校准模式。 接收器(900)将通过路径选择器输入的输出信号恢复为I / Q信号,以将恢复的信号提供给基带电路单元。

    전원 공급 장치 및 전원 공급 장치의 제어 방법
    63.
    发明公开
    전원 공급 장치 및 전원 공급 장치의 제어 방법 审中-实审
    用于控制电压供应装置的电源装置和方法

    公开(公告)号:KR1020160107481A

    公开(公告)日:2016-09-19

    申请号:KR1020150030259

    申请日:2015-03-04

    Inventor: 임준형

    CPC classification number: G05F3/02

    Abstract: 본발명의일 실시예에따른전원공급장치는, 기준전류를제공하는기준전류제공부; 기준전류에기초하여출력전압을출력하는전압출력부; 및온 상태일경우전압출력부에서발생되는전류를싱크(sink)하고출력전압이안정화된이후에오프상태가되는스위치부; 를포함함으로써, 안정적으로동작하면서전류소모를줄일수 있다.

    Abstract translation: 根据本发明实施例的电源装置包括提供参考电流的参考电流提供部分; 电压输出部,其基于所述参考电流输出输出电压; 以及开关部,其在导通状态的情况下吸收从电压输出部产生的电流,并且在输出电压稳定后变为截止。 由此,可以进行稳定的动作,能够降低电流消耗。

    광 센서 및 광 센서 장치
    64.
    发明公开
    광 센서 및 광 센서 장치 审中-实审
    光传感器和光传感器设备

    公开(公告)号:KR1020140081563A

    公开(公告)日:2014-07-01

    申请号:KR1020120151456

    申请日:2012-12-21

    CPC classification number: G01J1/0228 G01J1/0271 G01J1/44 G01J2001/446

    Abstract: The present invention relates to an optical sensor comprising a first light receiving element connected between an input terminal of an operating voltage and an output node and operating depending on incident light through a light receiving node; and a first capacitor circuit unit connected between the output node and a ground, wherein the first capacitor circuit unit performs a charging operation when the first light receiving element is in an ON state and performs a discharging operation when the first light receiving element is in an OFF state.

    Abstract translation: 光传感器技术领域本发明涉及一种光传感器,包括:连接在工作电压的输入端和输出节点之间的第一光接收元件,并根据入射光通过光接收节点进行操作; 以及连接在所述输出节点和地之间的第一电容器电路单元,其中,当所述第一光接收元件处于导通状态时,所述第一电容器电路单元执行充电操作,并且当所述第一光接收元件处于ON状态时,执行放电操作 OFF状态。

    드라이버 앰프 회로 및 그를 이용한 전력 증폭기
    65.
    发明公开
    드라이버 앰프 회로 및 그를 이용한 전력 증폭기 有权
    驱动放大器电路和功率放大器

    公开(公告)号:KR1020140045165A

    公开(公告)日:2014-04-16

    申请号:KR1020120111373

    申请日:2012-10-08

    CPC classification number: H03F3/217 H03F3/2171 H03K5/01

    Abstract: The present invention relates to a driver amplifier circuit and a power amplifier using the same. The driver amplifier circuit according to one embodiment of the present invention includes a filtering unit which shapes an input waveform by using a plurality of inverters which are connected in parallel, a delay unit which gives different delay to a plurality of output waveforms which are outputted from the inverters, and an output unit which overlaps the output waveforms which receive the different delay by the delay unit and outputs the overlapped result. Wherein, the filtering unit removes harmonic elements by using a voltage drop due to the internal resistance of the inverter.

    Abstract translation: 本发明涉及一种驱动放大器电路及使用其的功率放大器。 根据本发明的一个实施例的驱动器放大器电路包括:滤波单元,其通过使用并联连接的多个反相器对输入波形进行整形;延迟单元,其对从多个输出波形输出的多个输出波形给出不同的延迟 反相器和输出单元,其与由延迟单元接收不同延迟的输出波形重叠并输出重叠结果。 其中,滤波单元通过使用由于逆变器的内部电阻引起的电压降来去除谐波元件。

    RF 다이렉트 웨이크업 기능을 갖는 무선 통신 단말기 및 그의 웨이크업 방법
    66.
    发明公开
    RF 다이렉트 웨이크업 기능을 갖는 무선 통신 단말기 및 그의 웨이크업 방법 有权
    具有RF直接唤醒的无线通信终端及其唤醒方法

    公开(公告)号:KR1020130046855A

    公开(公告)日:2013-05-08

    申请号:KR1020110111495

    申请日:2011-10-28

    CPC classification number: H04W52/0235 Y02D70/166

    Abstract: PURPOSE: A wireless communication terminal including an RF(Radio Frequency) direct wakeup function is provided to execute a direct wakeup function by using an RFID(Radio Frequency Identification) without using a demodulation function. CONSTITUTION: An RF wakeup detection unit(100) detects a first RF signal including an RFID for a wakeup function. When the RFID included in the first RF signal detected by the RF wakeup detection unit is the same as a reference ID, a wireless communication unit(200) is woken up from a sleep mode. The RF wake-up detecting unit includes an RF rectifier and a level converter. The RF rectifier rectifies the first RF signal. The level converter converts the signal level of the rectifier into a signal level which can be recognized by the wireless communication unit. [Reference numerals] (110) RF rectifying unit; (120) Level conversion unit; (210) Communication unit; (220) Control unit

    Abstract translation: 目的:提供一种包括RF(射频)直接唤醒功能的无线通信终端,以通过使用RFID(射频识别)而不使用解调功能来执行直接唤醒功能。 构成:RF唤醒检测单元(100)检测包括用于唤醒功能的RFID的第一RF信号。 当由RF唤醒检测单元检测到的包含在第一RF信号中的RFID与参考ID相同时,无线通信单元(200)从睡眠模式唤醒。 RF唤醒检测单元包括RF整流器和电平转换器。 RF整流器整流第一RF信号。 电平转换器将整流器的信号电平转换成可由无线通信单元识别的信号电平。 (附图标记)(110)RF整流单元; (120)电平转换单元; (210)通讯单元; (220)控制单元

    역률 보상 제어 장치
    67.
    发明授权
    역률 보상 제어 장치 有权
    功率因数控制装置

    公开(公告)号:KR101251846B1

    公开(公告)日:2013-04-09

    申请号:KR1020110135596

    申请日:2011-12-15

    Abstract: PURPOSE: A power factor compensation control device is provided to reduce a manufacturing cost and to reduce the whole area by sharing an external comparator for a function signal with a comparator in an ADC(Analog-Digital Convertor). CONSTITUTION: A power factor compensation control unit(140) includes an inner voltage generating unit(141), a mux unit(142), an ADC(144), a digital operating unit(146), and an output unit(148). The inner voltage generating unit generates an external supply voltage(VDD) as an inner voltage(Vin) to provide the voltage to the digital operating unit. The mux unit muxes an input voltage(IAC) and an output voltage(IFB) to generate an ADC input signal(ADC_in). The ADC receives a function signal(Func_in) and the ADC input signal at the same time. The ADC selectively outputs one of the ADC input signal and the function signal based on a switch enable signal. The output unit generates a signal outputted from the digital operating unit as a control signal(GD) to provide the signal to the power factor compensation control unit. [Reference numerals] (141) Inner voltage generating unit; (142) Mux unit; (146) Digital operating unit; (148) Output unit;

    Abstract translation: 目的:提供功率因数补偿控制装置,通过与ADC(模拟数字转换器)中的比较器共享功能信号的外部比较器来降低制造成本并减少整个面积。 构成:功率因数补偿控制单元(140)包括内部电压产生单元(141),多路复用单元(142),ADC(144),数字操作单元(146)和输出单元(148)。 内部电压产生单元产生作为内部电压(Vin)的外部电源电压(VDD),以向数字操作单元提供电压。 复用单元将输入电压(IAC)和输出电压(IFB)复用以产生ADC输入信号(ADC_in)。 ADC同时接收功能信号(Func_in)和ADC输入信号。 ADC根据开关使能信号有选择地输出ADC输入信号和功能信号之一。 输出单元产生从数字操作单元输出的信号作为控制信号(GD),以向功率因数补偿控制单元提供信号。 (附图标记)(141)内电压发生单元; (142)复用单元; (146)数字操作单元; (148)输出单元;

    아날로그 디바이더
    68.
    发明授权

    公开(公告)号:KR101058698B1

    公开(公告)日:2011-08-22

    申请号:KR1020090024387

    申请日:2009-03-23

    Abstract: 본 발명에 따른 아날로그 디바이더는, DC 블로킹 커패시터를 통해 입력 신호에 포함된 제 1 DC 오프셋을 제거하고, 저항과 인버터를 통해 미리 정해진 제 2 DC 오프셋을 상기 제 1 DC 오프셋이 제거된 입력 신호에 결합하는 선형 제어 블록; 상기 선형 제어 블록을 통과한 신호의 주기를 분주하는 디바이더 코어; 상기 디바이더 코어의 출력 신호를 인가받아 증폭시키는 출력 버퍼; 를 포함할 수 있다.
    오프셋, 인버터, 출력 버퍼, DC 블로킹 커패시터, 저항

    저전력용 직류 검출기
    69.
    发明授权
    저전력용 직류 검출기 失效
    直流电流检测器,用于低功耗

    公开(公告)号:KR101004815B1

    公开(公告)日:2010-12-28

    申请号:KR1020080078011

    申请日:2008-08-08

    Inventor: 임준형 박타준

    CPC classification number: G01R19/16542

    Abstract: 본 발명은 저전력용 직류 검출기에 관한 것으로, 극소 전류를 생성하는 메인 전류원 회로부; 상기 메인 전류원 회로부에 의해 생성되는 전류를 기설정된 전류 이하로 제한하는 제한 회로부; 및 상기 메인 전류원 회로부에 의해 생성된 극소 전류에 의해 바이어싱 되어, 입력되는 직류 전압을 검출하는 전압 검출 회로부를 포함한다.
    저전력, 극소전류, 웨이크업, 수신기, 직류, 검출

    시스템온칩 플래쉬 메모리 보호 회로
    70.
    发明公开
    시스템온칩 플래쉬 메모리 보호 회로 无效
    闪存系统中的闪存保护电路

    公开(公告)号:KR1020100130074A

    公开(公告)日:2010-12-10

    申请号:KR1020090048736

    申请日:2009-06-02

    CPC classification number: G11C16/20 G11C7/20 G11C7/24 G11C16/22

    Abstract: PURPOSE: A system-on chip flash memory protection circuit is provided to protect the memory of system-on chip by enforcing to reset the system-on chip during the predetermined time at the point of power-up. CONSTITUTION: A load(100) is connected between an output terminal(T1) and the ground. A delay unit(200) delays the state voltage(Vs) applied to the load as long as the predetermined delay time. A delay detection unit(300) detects the point of time when the delay voltage(Vd) delayed by the delay unit is shifted to the high level.

    Abstract translation: 目的:提供片上系统闪存保护电路,通过在上电时的预定时间内执行芯片上的系统复位来保护片上系统的存储器。 构成:负载(100)连接在输出端子(T1)和地之间。 延迟单元(200)只要预定的延迟时间延迟施加到负载的状态电压(Vs)。 延迟检测单元(300)检测延迟单元延迟的延迟电压(Vd)向高电平移动的时间点。

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