公开(公告)号：KR1020050028713A

公开(公告)日：2005-03-23

申请号：KR1020030065226

申请日：2003-09-19

Applicant: 삼성전자주식회사

Inventor： 강인구 ,  윤성환

IPC: H01L23/12

CPC classification number: H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L29/0657 ,  H01L2224/05647 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/49113 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/10155 ,  H01L2924/10158 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/4554

Abstract: A semiconductor package is provided to fabricate a light thin mobile electronic instrument by decreasing the thickness of a single chip semiconductor package and by making the semiconductor package lighter. A connection pad(202) is formed at the edge of the upper surface of a substrate. A semiconductor chip(220b) is attached to the substrate by insulating adhesive(234) in a manner that the active surface of the substrate faces the substrate, including a base part and a protrusion part protruding from the base part to an opposite direction to the substrate. The active surface formed on the bottom of the base part includes an inner bonding pad and a conductive pattern extending from the inner bonding pad to both side surfaces of the base part. An outer bonding pad(250b) is connected to the conductive pattern at both side ends of the base part having no protrusion part, and the upper surface of the outer bonding pad is exposed to the opposite side to the substrate. The exposed surface of the outer bonding pad is connected to the connection pad by a wire(214).

Abstract translation: 提供半导体封装以通过减小单个芯片半导体封装的厚度并使半导体封装更轻，来制造轻薄的移动电子仪器。 在衬底的上表面的边缘处形成连接衬垫（202）。 半导体芯片（220b）通过绝缘粘合剂（234）以基板的有效表面面向基板的方式附着到基板，该基板部分和从基部突出到与该基板相反的方向的突出部分 基质。 形成在基部的底部上的有源面包括内接合焊盘和从内焊盘延伸到基部的两个侧表面的导电图案。 外部接合焊盘（250b）在没有突出部的基部的两个侧端处连接到导电图案，并且外部接合焊盘的上表面暴露于与基板相反的一侧。 外焊盘的暴露表面通过导线（214）连接到连接焊盘。

公开(公告)号：KR1020050023972A

公开(公告)日：2005-03-10

申请号：KR1020030061760

申请日：2003-09-04

Applicant: 삼성전자주식회사

Inventor： 김진호 ,  강인구 ,  이상엽

IPC: H01L21/60

CPC classification number: H01L24/85 ,  H01L24/45 ,  H01L24/48 ,  H01L24/78 ,  H01L2224/02126 ,  H01L2224/02166 ,  H01L2224/05554 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4809 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48472 ,  H01L2224/48479 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/78301 ,  H01L2224/85045 ,  H01L2224/85051 ,  H01L2224/85181 ,  H01L2224/85205 ,  H01L2224/85951 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2224/4554 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: PURPOSE: A wire-bonding method of a semiconductor device is provided to minimize the time necessary for wire-bonding by minimizing a moving path of a capillary using two-step stitch bonding. CONSTITUTION: A semiconductor chip(10) with bonding pads(12) is mounted on a PCB(Printed Circuit Board)(20) with leads(22). At this time, the bonding pad approximates to the lead. A ball bump(42) is formed on the bonding pad by using a cut portion of a bonding wire(40). First stitch bonding is performed on the ball bump by using one end of the bonding wire. Second stitch bonding is performed on the lead by using the other end of the bonding wire.

Abstract translation: 目的：提供半导体器件的引线接合方法，以通过使用两步缝合结合使毛细管的移动路径最小化来最小化引线接合所需的时间。 构成：具有接合焊盘（12）的半导体芯片（10）通过引线（22）安装在PCB（印刷电路板）（20）上。 此时，焊盘靠近引线。 通过使用接合线（40）的切割部分在接合焊盘上形成球凸块（42）。 通过使用接合线的一端在球凸点上进行第一缝合。 通过使用接合线的另一端在引线上进行第二缝合。

公开(公告)号：KR1020050012507A

公开(公告)日：2005-02-02

申请号：KR1020030051490

申请日：2003-07-25

Applicant: 삼성전자주식회사

Inventor： 윤성환 ,  김진호 ,  강인구

IPC: H01L21/60

CPC classification number: H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/00

Abstract: PURPOSE: A Wire bonding method for a stacked chip package is provided to obtain a stable wire bonding by forming a bump with good joining capability. CONSTITUTION: A first chip(24) is attached on a substrate(22). The first chip and the substrate are electrically connected by a first bonding wire(23). A second chip(26) having a bump(28) formed on a chip pad(27) is attached on the first chip, and a portion having the bump on the second chip is located at the outside of the first chip. A bump on the second chip and the substrate are electrically connected by a second bonding wire(25).

Abstract translation: 目的：提供一种用于堆叠芯片封装的引线接合方法，通过形成具有良好接合能力的凸块来获得稳定的引线接合。 构成：第一芯片（24）附着在基板（22）上。 第一芯片和基板通过第一接合线（23）电连接。 具有形成在芯片焊盘（27）上的突起（28）的第二芯片（26）安装在第一芯片上，并且具有位于第二芯片上的凸块的部分位于第一芯片的外部。 第二芯片和基板上的凸块通过第二接合线（25）电连接。

公开(公告)号：KR1020030034491A

公开(公告)日：2003-05-09

申请号：KR1020010065445

申请日：2001-10-23

Applicant: 삼성전자주식회사

Inventor： 강인구

IPC: H01L21/68

Abstract: PURPOSE: A semiconductor fabricating apparatus having a substrate detecting apparatus is provided to prevent an unpredicted process error caused by misalignment of a semiconductor substrate by installing a plurality of substrate detecting apparatuses composed of a light emitting unit and a light receiving unit in a cover member and a support body. CONSTITUTION: A substrate supporting unit on which the semiconductor substrate(100) is placed is included in the supporting body(120). The cover member(110) is coupled to the supporting unit or is separated from the supporting unit. A reaction chamber(10) includes the supporting body and the cover member. At least one substrate detecting apparatus(130) can detect the semiconductor substrate positioned on the substrate supporting unit, installed in each side of the supporting body and the cover member.

Abstract translation: 目的：提供一种具有基板检测装置的半导体制造装置，用于通过将由发光单元和光接收单元组成的多个基板检测装置安装在盖部件中来防止由于半导体基板的未对准而引起的不可预测的处理误差， 一个支撑体 构成：其上放置有半导体衬底（100）的衬底支撑单元包括在支撑体（120）中。 盖构件（110）联接到支撑单元或者与支撑单元分离。 反应室（10）包括支撑体和盖构件。 至少一个基板检测装置可以检测位于基板支撑单元上的半导体基板，该基板支撑单元安装在支撑体的每一侧和盖构件中。

公开(公告)号：KR1020030008616A

公开(公告)日：2003-01-29

申请号：KR1020010043446

申请日：2001-07-19

Applicant: 삼성전자주식회사

Inventor： 강인구 ,  안상호

IPC: H01L23/495

CPC classification number: H01L23/3107 ,  H01L21/4832 ,  H01L23/49548 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05553 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85001 ,  H01L2224/85411 ,  H01L2224/85444 ,  H01L2224/85464 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: PURPOSE: A bumped chip carrier package using a lead frame and a method for fabricating the same are provided to prevent a damage of an external connection terminal by forming a resin sealing portion. CONSTITUTION: A lead frame is provided. The lead frame has a chip mounting region(62) and a plurality of internal connection terminals(64) projected to the outside of the chip mounting region(62). A semiconductor chip(70) having a plurality of electrode pads is adhered on the chip mounting region(62). The electrode pads of the semiconductor chip(70) are electrically connected with the internal connection terminals(64) by using a bonding wire(80). A resin sealing portion(90) is formed by applying molding resin on the semiconductor chip(70), the bonding wire(80), and the internal connection terminals(64). An external connection terminal(68) is formed by removing the lead frame except for a lower part of the internal connection terminal(64).

Abstract translation: 目的：提供使用引线框架的凸起的芯片载体封装及其制造方法，以通过形成树脂密封部分来防止外部连接端子的损坏。 构成：提供引线框架。 引线框架具有芯片安装区域（62）和突出到芯片安装区域（62）的外部的多个内部连接端子（64）。 具有多个电极焊盘的半导体芯片（70）粘附在芯片安装区域（62）上。 通过使用接合线（80），半导体芯片（70）的电极焊盘与内部连接端子（64）电连接。 通过在半导体芯片（70），接合线（80）和内部连接端子（64）上施加模制树脂来形成树脂密封部分（90）。 通过除去除了内部连接端子（64）的下部以外的引线框架，形成外部连接端子（68）。

公开(公告)号：KR1020020067146A

公开(公告)日：2002-08-22

申请号：KR1020010007546

申请日：2001-02-15

Applicant: 삼성전자주식회사

Inventor： 강인구 ,  김길용 ,  김수현 ,  윤명호 ,  이경수

IPC: H01L21/68

Abstract: PURPOSE: A teaching tool of a wafer transfer arm is provided to prevent inaccurate teaching of a wafer, by obtaining accurate teaching data of a transfer arm through a bar of the teaching tool and by loading/unloading the wafer to a state while using the accurate teaching data. CONSTITUTION: A body(100) has the same type and size as the wafer. A center identifying unit is installed in the center of the body to adjust the center of the stage(200) on which the wafer is to be placed. The bar(120) is installed in the center of the bottom surface of the body. The bar is made of a transparent quartz material, having a length of 17 millimeter.

Abstract translation: 目的：提供晶片传送臂的教学工具，通过通过教学工具的杆获得传递臂的精确教学数据，并通过将晶片加载/卸载到状态，同时使用准确的 教学数据。 构成：主体（100）具有与晶片相同的类型和尺寸。 中心识别单元安装在身体的中心，以调整要放置晶片的台（200）的中心。 杆（120）安装在主体的底面的中心。 该条由透明的石英材料制成，长度为17毫米。

公开(公告)号：KR1020020061813A

公开(公告)日：2002-07-25

申请号：KR1020010002830

申请日：2001-01-18

Applicant: 삼성전자주식회사

Inventor： 강인구 ,  이관재

IPC: H01L21/60

CPC classification number: H01L2224/16 ,  H01L2924/15311

Abstract: PURPOSE: A semiconductor chip package having dual bumps is provided to prevent a semiconductor chip and a substrate from being easily separated from each other while the semiconductor is attached to the substrate only by a bump, and to stably perform an electrical connection between the semiconductor chip and the substrate. CONSTITUTION: The substrate(103) has an upper surface on which solder balls(109) are formed and a lower surface opposite to the lower surface. The semiconductor chip(101) has an active surface having a bonding pad(111) and an inactive surface opposite to the active surface. The first bump(107a) is formed on the upper surface. The second bump(107b) is formed in the bonding pad. A part of the first bump is positioned inside the second bump. An insulation layer(115) is formed on the active surface where the second bump is not formed. An encapsulating unit(105) is so formed to expose the inactive surface so that the first and second bumps are protected.

Abstract translation: 目的：提供具有双凸块的半导体芯片封装，以防止半导体芯片和基板彼此分离，同时半导体仅通过凸块附接到基板，并且稳定地执行半导体芯片之间的电连接 和基板。 构成：衬底（103）具有形成焊球（109）的上表面和与下表面相对的下表面。 半导体芯片（101）具有具有接合焊盘（111）的活性表面和与活性表面相对的非活性表面。 第一凸起（107a）形成在上表面上。 第二突起（107b）形成在接合焊盘中。 第一凸块的一部分位于第二凸块的内部。 在没有形成第二凸块的活性表面上形成绝缘层（115）。 封装单元（105）被形成为暴露非活性表面，使得第一和第二凸块被保护。

公开(公告)号：KR1020020030891A

公开(公告)日：2002-04-26

申请号：KR1020000061238

申请日：2000-10-18

Applicant: 삼성전자주식회사

Inventor： 이관재 ,  강인구

IPC: H01L23/12

Abstract: PURPOSE: A stack package using a flexible substrate is provided to stack packages regardless of the size of a semiconductor chip, by folding the semiconductor chip tab-bonded and flip-chip bonded to the flexible substrate to form the stack package. CONSTITUTION: The second tab bonding region(14) is folded to confront the first tab bonding region(12), connected to the first tab bonding region and separated from the first tab bonding region by a predetermined distance. A flip-chip bonding region(16) is folded to confront the second tab bonding region, connected to the first tab bonding region in a direction vertical to the direction that the first and second tab bonding regions are connected. The flexible(10) substrate includes the first tab bonding region, the second tab bonding region and the flip-chip bonding region. The first chip(20) is tab-bonded to the first tab bonding region between the folded first and second tab bonding regions. The second chip(30) is tab-bonded to the second tab bonding region, and the back surface of the second chip is attached to the back surface of the first chip. The third chip(40) is flip-chip bonded to the flip-chip region of the flexible substrate, and the back surface of the third chip is attached to a surface opposite to the second tab bonding region to which the second chip is flip-chip bonded. A plurality of external connection terminals are formed on a surface opposite to the flip-chip bonding region to which the third chip is bonded.

Abstract translation: 目的：通过将半导体芯片片状结合和倒装芯片折叠到柔性基板上以形成堆叠封装，提供使用柔性基板的堆叠封装堆叠封装，而不管半导体芯片的尺寸如何。 构成：将第二突片接合区域（14）折叠成与第一突片接合区域（12）相对，连接到第一突片接合区域并与第一突片接合区域分离预定距离。 折叠接合区域（16）被折叠以面对与第一和第二接合区域连接的方向垂直的方向连接到第一接头接合区域的第二接头接合区域。 柔性（10）衬底包括第一接片接合区域，第二接头接合区域和倒装芯片接合区域。 第一芯片（20）与折叠的第一和第二接头接合区域之间的第一接片接合区域接合。 第二芯片（30）与第二接头接合区域接合，第二芯片的背面安装在第一芯片的背面。 第三芯片（40）被倒装芯片接合到柔性基板的倒装芯片区域，并且第三芯片的背面安装在与第二芯片翻转的第二引脚接合区域相对的表面上， 芯片贴合。 在与第三芯片接合的倒装芯片接合区域相对的表面上形成多个外部连接端子。

公开(公告)号：KR1020010027266A

公开(公告)日：2001-04-06

申请号：KR1019990038943

申请日：1999-09-13

Applicant: 삼성전자주식회사

Inventor： 이관재 ,  조태제 ,  강인구

IPC: H01L23/28

Abstract: PURPOSE: A stacking package is provided to increase a capacity and density of a package by applying a BGA(Ball Grid Array) package method. CONSTITUTION: A stacking package(10) is piled up two unit semiconductor chip packages(10a,10b), containing a PCB(20a,20b). An upper circuit pattern(21a,21b), and a lower circuit pattern(22a,22b) are formed in each unit semiconductor chip package(10a,10b). The upper circuit pattern(21a,21b) and the lower circuit pattern(22a,22b) are connected by a via(23a,23b) through the PCB(20a,20b). In the center of the PCB(20a,20b), a cavity(24a,24b) is made, and a slot(25a,25b), passing through lower part of the cavity(24a,24b), is built. A center pad type of semiconductor chip(30a,30b) is attached on the cavity(24a,24b). An active region of the semiconductor chip(30a,30b) is bound on the PCB(20a,20b), and an electrode pad(31a,31b) is located on the slot(25a,25b). The electrode pad(31a,31b) is wire bound with the lower circuit pattern(22a,22b) using a conductive metal wire(40a,40b) through the slot(25a,25b). A solder ball(70a,70b) is adhered on the lower circuit pattern(22a,22b) as an outer contact electrode. A compound part(60a,60b) protects the semiconductor chip(30a,30b) and the conductive metal wire(40a,40b). The upper unit chip package(10a) and the lower unit chip package(10b) are connected and stacked by the solder ball(70a) of the upper unit chip package(10a) touching the upper circuit pattern(21b) of the lower unit chip package(10b).

Abstract translation: 目的：提供堆叠包装，通过应用BGA（球栅阵列）封装方法提高封装的容量和密度。 构成：堆叠封装（10）堆叠包含PCB（20a，20b）的两个单元半导体芯片封装（10a，10b）。 在每个单位半导体芯片封装（10a，10b）中形成上电路图案（21a，21b）和下电路图案（22a，22b）。 上电路图案（21a，21b）和下电路图案（22a，22b）通过通孔（23a，23b）通过PCB（20a，20b）连接。 在PCB（20a，20b）的中心形成有空腔（24a，24b），并且构成通过空腔（24a，24b）的下部的槽（25a，25b）。 中空衬垫型半导体芯片（30a，30b）安装在空腔（24a，24b）上。 半导体芯片（30a，30b）的有源区域结合在PCB（20a，20b）上，电极焊盘（31a，31b）位于槽（25a，25b）上。 电极焊盘（31a，31b）利用导电金属线（40a，40b）通过槽（25a，25b）与下电路图案（22a，22b）线接合。 焊球（70a，70b）作为外接触电极粘附在下电路图案（22a，22b）上。 复合部件（60a，60b）保护半导体芯片（30a，30b）和导电金属线（40a，40b）。 上单元芯片封装（10a）和下单元芯片封装（10b）通过接触下单元芯片的上电路图案（21b）的上单元芯片封装（10a）的焊球（70a）连接和堆叠 包（图10b）。

公开(公告)号：KR1020010017144A

公开(公告)日：2001-03-05

申请号：KR1019990032516

申请日：1999-08-09

Applicant: 삼성전자주식회사

Inventor： 심종보 ,  강인구

IPC: H01L23/14

Abstract: PURPOSE: A method for manufacturing a carrier tape for a stacked flip chip package is provided to achieve high reliability. CONSTITUTION: A bottom adhesive film is prepared for insulating a semiconductor chip(10). A metal film is adhered to the bottom adhesive film(20). A pattern is formed to make a bump connection unit on the metal film(30). Then an upper adhesive film is adhered to the on the metal film(40). The upper/bottom adhesive film is used as an ASF(anisotropic conductive film) having uniform conductive particles or an insulative adhesive film.

Abstract translation: 目的：提供一种用于制造用于堆叠倒装芯片封装的载带的方法，以实现高可靠性。 构成：制备用于绝缘半导体芯片（10）的底部粘合剂膜。 金属膜粘附到底部粘合膜（20）上。 形成图案以在金属膜（30）上形成凸块连接单元。 然后在金属膜（40）上粘附上粘合膜。 上/下粘合膜用作具有均匀导电颗粒或绝缘粘合剂膜的ASF（各向异性导电膜）。