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公开(公告)号：KR101852989B1
公开(公告)日：2018-04-30
申请号：KR1020110040140
申请日：2011-04-28
Applicant: 삼성전자주식회사
CPC classification number: G02F1/133 , H01L23/3121 , H01L24/73 , H01L2224/16225 , H01L2224/32225 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2924/01322 , H01L2924/3025 , H01L2924/00012 , H01L2924/00
Abstract: 본발명은정전기나기타전기적충격으로부터반도체칩을보호할수 있게하는반도체패키지장치에관한것으로서, 반도체칩; 상기반도체칩을지지하는기판; 상기기판에형성되고, 상기반도체칩과전기적으로연결되는적어도하나의단자; 임계전압이인가되면절연성에서도전성으로변하는감전압성물질(voltage sensitive material)을포함하여이루어지고, 상기반도체칩을둘러싸서보호하는제 1 봉지재; 상기제 1 봉지재에인가된정전기를외부로유도하는정전기유도단자; 및상기제 1 봉지재와상기정전기유도단자사이에설치되고, 상기정전기를상기정전기유도단자로유도하는정전기차단부재;를포함한다.
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公开(公告)号：KR1020130105163A
公开(公告)日：2013-09-25
申请号：KR1020120027359
申请日：2012-03-16
Applicant: 삼성전자주식회사
IPC: H01L23/60
CPC classification number: H01L23/5256 , H01L23/4985 , H01L23/60 , H01L2924/0002 , H02H9/041 , H01L2924/00
Abstract: PURPOSE: A semiconductor package and a display device including the same are provided to distribute static electricity to a ground layer or to output the static electricity to the outside by including a via contact which electrically connects a wiring pattern to the ground layer in a non-mounting area. CONSTITUTION: A base film (20) has a first surface and a second surface which faces the first surface. The base film is composed of a first area and a second area. A wiring pattern is formed on the first surface of the base film in the second area. An insulation layer (26) is arranged on the wiring pattern of the second area. A ground layer (28) is arranged on the second surface of the base film. A semiconductor chip (10) is mounted on the first surface of the base film in the first area.
Abstract translation: 目的：提供一种半导体封装和包括该半导体封装的显示装置，用于将静电分配到接地层，或通过包括以非导电方式将布线图案与接地层电连接的通孔接点将静电输出到外部， 安装区域。 构成：基膜（20）具有面向第一表面的第一表面和第二表面。 基膜由第一区域和第二区域构成。 在第二区域中的基膜的第一表面上形成布线图案。 绝缘层（26）布置在第二区域的布线图案上。 接地层（28）布置在基膜的第二表面上。 半导体芯片（10）安装在第一区域的基膜的第一表面上。
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公开(公告)号：KR1020030025696A
公开(公告)日：2003-03-29
申请号：KR1020010058866
申请日：2001-09-22
Applicant: 삼성전자주식회사
Inventor： 이관재
IPC: H01L21/56
CPC classification number: H01L2224/50
Abstract: PURPOSE: A semiconductor chip package having a base film is provided to prevent deformation of leads in a fabrication process of the semiconductor chip package by using the base film for supporting the leads. CONSTITUTION: A plurality of bonding pads are formed on a semiconductor chip(2). A plurality of leads(4) are arrayed on an upper portion of the bonding pads of the semiconductor chip(2). A conductive adhesive portion is inserted between the bonding pads of the semiconductor chip(2) and the leads(4). A base film(6) is used for supporting the leads(4). The base film(6) includes a center hole(20), a curved hole(22), and a slit(24). The center hole(20) is formed with a rectangular shape. The center hole(20) is extended to each end of the leads(4). The curved hole(22) is formed on an idle region of the base film(6). The slit(24) is used for connecting the center hole(20) with the curved hole(22).
Abstract translation: 目的：提供具有基膜的半导体芯片封装，以通过使用用于支撑引线的基膜来防止半导体芯片封装的制造工艺中引线的变形。 构成：在半导体芯片（2）上形成多个接合焊盘。 多个引线（4）排列在半导体芯片（2）的接合焊盘的上部。 导电粘合剂部分插入在半导体芯片（2）的接合焊盘和引线（4）之间。 底片（6）用于支撑引线（4）。 基膜（6）包括中心孔（20），弯曲孔（22）和狭缝（24）。 中心孔（20）形成为矩形。 中心孔（20）延伸到引线（4）的每一端。 弯曲孔（22）形成在基膜（6）的空闲区域上。 狭缝（24）用于将中心孔（20）与弯曲孔（22）连接起来。
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公开(公告)号：KR1020020061812A
公开(公告)日：2002-07-25
申请号：KR1020010002828
申请日：2001-01-18
Applicant: 삼성전자주식회사
IPC: H01L23/12
CPC classification number: H01L2224/16227 , H01L2224/26175 , H01L2224/32225 , H01L2224/32245 , H01L2224/48247 , H01L2224/73204 , H01L2224/73265 , H01L2225/1023 , H01L2225/1058 , H01L2924/15311 , H01L2924/15331 , H01L2924/00012
Abstract: PURPOSE: A multichip package of a ball grid array(BGA) type is provided to double the capacity in the same area by stacking two semiconductor chips, and to effectively correspond to an increase of the number of input/output pins by using a printed circuit board(PCB). CONSTITUTION: Predetermined circuit interconnections(22,26) and connection pads(23,27) connected to the circuit interconnections are formed on the upper and lower surfaces of a base substrate(21). A via hole(25) for electrically connecting the circuit interconnection on the upper surface with the circuit interconnection on the lower surface is formed in a PCB(20). The first and second chips have a plurality of electrode pads(12,16) formed on an active surface having an integrated circuit and bumps(13,17) connected to the electrode pads. The bump of the first chip is connected to the connection pad formed on the upper surface of the PCB. The bump of the second chip is connected to the connection pad formed on the lower surface of the PCB. Solder balls(45) are electrically connected to the circuit interconnection formed on a surface of the PCB.
Abstract translation: 目的：提供一种球栅阵列（BGA）类型的多芯片封装，通过堆叠两个半导体芯片使相同区域的容量增加一倍，并通过使用印刷电路有效地对应于输入/输出引脚数量的增加 板（PCB）。 构成：连接到电路互连的预定电路互连（22,26）和连接焊盘（23,27）形成在基底（21）的上表面和下表面上。 用于将上表面上的电路互连与下表面上的电路互连电连接的通孔（25）形成在PCB（20）中。 第一和第二芯片具有形成在具有集成电路的有源表面上的多个电极焊盘（12,16）和连接到电极焊盘的凸块（13,17）。 第一芯片的凸起连接到形成在PCB的上表面上的连接焊盘。 第二芯片的凸起连接到形成在PCB的下表面上的连接焊盘。 焊球（45）电连接到形成在PCB的表面上的电路互连。
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Patent Agency Ranking
公开(公告)号：KR1020020039012A
公开(公告)日：2002-05-25
申请号：KR1020000068884
申请日：2000-11-20
Applicant: 삼성전자주식회사
IPC: H01L23/12
CPC classification number: H01L2224/4824 , H01L2924/181 , H01L2924/00012
Abstract: PURPOSE: A stacked semiconductor chip package using a chip select terminal of the same type is provided to embody the stacked semiconductor chip package without an additional process, by making a chip select pad of each semiconductor chip correspond to each chip select terminal in the order that the respective semiconductor chips are stacked through a stacked substrate. CONSTITUTION: A predetermined number of semiconductor chips have bonding pads(214) including the chip select pad(212). The stacked substrates(220) have an upper surface(222) and a lower surface(224). The respective semiconductor chips are mounted on the upper surface having upper pads(232,252) uniformly disposed with respect to the semiconductor chip. Lower pads(234,254) are formed along the vertical axis passing through the respective upper pads, electrically and correspondingly connected to the upper pads. Connection terminals are formed on the respective lower pads, electrically connected to the lower pads. The chip select terminal is composed of a predetermined number of consecutive pairs of respective stacked substrates so that an arbitrary upper pad is electrically connected to its next lower pad with respect to the order that the upper pads are disposed. The chip select pad of each semiconductor chip is electrically connected to the first lower pad of the chip select terminal of the stacked substrate corresponding to the chip select pad. The chip select pad of each semiconductor chip corresponds to the chip select terminal of the stacked substrate according to the order that the stacked substrates on which the semiconductor chip is mounted are stacked.
Abstract translation: 目的：提供使用相同类型的芯片选择端子的堆叠半导体芯片封装，以便通过使每个半导体芯片的芯片选择焊盘对应于每个芯片选择端子来实现叠层半导体芯片封装，而不需要额外的工艺，其顺序为 各个半导体芯片通过堆叠的衬底堆叠。 构成：预定数量的半导体芯片具有包括芯片选择焊盘（212）的接合焊盘（214）。 堆叠的基板（220）具有上表面（222）和下表面（224）。 相应的半导体芯片安装在具有相对于半导体芯片均匀设置的上焊盘（232,252）的上表面上。 下焊盘（234,254）沿着穿过相应的上焊盘的垂直轴线形成，电和相应地连接到上焊盘。 连接端子形成在相应的下垫上，电连接到下垫。 芯片选择端子由预定数量的连续成对的各个堆叠的基板组成，使得任意的上焊盘相对于设置上焊盘的顺序与其下一个下焊盘电连接。 每个半导体芯片的芯片选择焊盘电连接到对应于芯片选择焊盘的堆叠衬底的芯片选择端子的第一下焊盘。 每个半导体芯片的芯片选择焊盘根据叠层有半导体芯片的层叠基板的顺序对应于层叠基板的芯片选择端子。
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公开(公告)号：KR1020010060872A
公开(公告)日：2001-07-07
申请号：KR1019990063330
申请日：1999-12-28
Applicant: 삼성전자주식회사
IPC: H01L23/28
CPC classification number: H01L2224/4826 , H01L2224/73215 , H01L2924/181 , H01L2924/00012
Abstract: PURPOSE: A semiconductor chip package and manufacturing method is provided to enable easy layering with small thickness by using a lead frame. CONSTITUTION: Tie bars(25) and leads(21) are arranged with a uniform interval around a semiconductor chip(11) having an integrated circuit. Edge pad type bonding pads(12) are formed at both edges of the semiconductor chip(11). The leads(21) are bidirectionally arranged with internal tips being opposed to each other. The tie bars(25) are a pair to perpendicularly intersect with the leads(21) at both directions. Each of the leads(21) has a lead step portion(22) stepped with a certain height from the upper surface in the inner tip. Each of the tie bars(25) has a tie bar step portion(26) stepped with a certain height to be positioned flush with the upper surface of the semiconductor chip(11). The semiconductor chip(11) is fixed by adhering tapes(30) attached to the tie bars(25).
Abstract translation: 目的：提供一种半导体芯片封装和制造方法，以通过使用引线框使得能够以小的厚度进行易于分层。 构成：在具有集成电路的半导体芯片（11）周围以均匀的间隔布置带状条（25）和引线（21）。 边缘焊盘型接合焊盘（12）形成在半导体芯片（11）的两个边缘处。 引线（21）是双向布置的，内部尖端彼此相对。 连杆（25）是在两个方向上与引线（21）垂直相交的对。 每个引线（21）具有从内端部的上表面以一定高度台阶的引线台阶部（22）。 每个连接杆（25）具有以一定高度阶梯形的衔铁条台阶部分（26），以与半导体芯片（11）的上表面齐平。 半导体芯片（11）通过粘附在连接条（25）上的带（30）固定。
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公开(公告)号：KR100265460B1
公开(公告)日：2000-09-15
申请号：KR1019950038149
申请日：1995-10-30
Applicant: 삼성전자주식회사
IPC: H01L23/495
CPC classification number: H01L2224/32245
Abstract: PURPOSE: A lead frame is to prevent bending or twisting of a die pad by bumping the stresses caused by bending of a tie bar and the difference of thermal expansion between the die pad and a semiconductor chip and to improve reliability of the chip. CONSTITUTION: A connecting part(45) is integrally connected to a tie bar(42). A buffering part(43) integrally connected between the connecting parts has an opening(44) therein. The opening has many unevenness on a side parallel to a direction of the tie bar while the buffering part has unevenness on its outside in correspondence to the unevenness of the opening. The unevenness on the buffering part projects perpendicular to the direction of the tie bar and has a triangular, saw tooth, rectangular or curved wave form. Intrinsic stress of the tie bar due to a bending operation for the tie bar at the die pad is transmitted to the die pad along the connecting direction of the tie bar. When a semiconductor chip having a long side in a direction of the tie bar is attached to the die pad, stress propagates to mainly in a tie bar direction.
Abstract translation: 目的：引线框架是通过碰撞由拉杆的弯曲引起的应力和芯片焊盘与半导体芯片之间的热膨胀差异来提高芯片的弯曲或扭曲，并提高芯片的可靠性。 构成：连接部分（45）与连杆（42）一体地连接。 整体连接在连接部件之间的缓冲部件（43）在其中具有开口（44）。 开口在平行于拉杆的方向的一侧具有许多不均匀性，而缓冲部分在其外侧具有与开口的不均匀性相对应的凹凸。 缓冲部分的凹凸垂直于拉杆的方向突出并具有三角形，锯齿形，矩形或弯曲波形。 因连接杆在管芯焊盘处的弯曲操作引起的拉杆的固有应力沿着连接杆的连接方向被传递到管芯焊盘。 当在连接杆的方向上具有长边的半导体芯片附接到管芯焊盘时，应力传播到主要的拉杆方向。
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公开(公告)号：KR1019990050825A
公开(公告)日：1999-07-05
申请号：KR1019970070013
申请日：1997-12-17
Applicant: 삼성전자주식회사
IPC: H01L23/36
Abstract: 본 발명은 고 열방출 리드 프레임 및 이를 이용한 반도체 패키지에 관한 것이다. 본 발명의 목적은 반도체 패키지의 효과적인 열 방출을 위한 방열 리드가 리드 프레임과 일체형으로 다이 패드 주위에 형성된 리드 프레임과 이를 이용한 반도체 패키지를 제공하는 데 있다. 이러한 목적을 달성하기 위하여 본 발명은 내부 리드 중의 일부가 연장되어 다이 패드와 내부 리드의 사이에서 다이 패드 및 내부 리드와 각각 이격되어 다이 패드 주위를 둘러싸는 방열 리드를 구비하는 고 열방출 리드 프레임과 이와 같은 리드 프레임을 이용한 고 열방출 반도체 패키지를 제공한다. 본 발명에 의하면, 리드 프레임을 제조하는 공정에서 리드 프레임과 일체형으로 방열 리드를 제공하므로, 반도체 칩을 패키징할 때 별도의 방열 리드를 부착 또는 삽입하는 공정에 비해서 리드 프레임 제조 비용을 감소시키고, 패키징 공정을 단순화시킬 수 있다.
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