公开(公告)号：KR100487529B1

公开(公告)日：2005-05-03

申请号：KR1020020040716

申请日：2002-07-12

Applicant: 삼성전자주식회사

Inventor： 민병준 ,  김기남 ,  전병길 ,  최문규

IPC: G11C29/00

Abstract: 높은 효율을 갖는 반도체 메모리 장치의 불량 셀 구제 기술이 여기에 개시된다. 모든 메모리 블록들의 동일한 행에서 불량 셀이 발생할 경우, 하나의 리던던시 디코더를 구동하여 불량 셀이 발생한 특정 행을 해당 리던던시 행으로 대체하고, 특정 메모리 블록에서만 불량 셀이 발생할 경우, 입력되는 주소가 불량 셀이 발생한 특정 블록을 지정할 때 해당 리던던시 디코더를 구동하여 불량 셀을 구제한다. 또 인접한 K개의 메모리 블록들의 동일한 행에서 불량 셀이 발생할 경우, 하나의 리던던시 디코더를 구동하여 불량 셀들을 구제한다. 인접하지 않은 블록들의 동일한 행에서 불량 셀이 발생할 경우, 하나의 리던던시 디코더를 사용하거나 또는 해당 블록에 대응하는 리던던시 디코더들을 사용하여 불량 셀을 구제한다.

公开(公告)号：KR100456698B1

公开(公告)日：2004-11-10

申请号：KR1020020053116

申请日：2002-09-04

Applicant: 삼성전자주식회사

Inventor： 김기남 ,  송윤종 ,  주흥진

IPC: H01L27/105

CPC classification number: H01L27/11502 ,  H01L27/11507

Abstract: Methods for forming an electronic device can include forming a capacitor structure on a portion of a substrate with the capacitor structure including a first electrode on the substrate, a capacitor dielectric on the first electrode, a second electrode on the dielectric, and a hard mask on the second electrode. More particularly, the capacitor dielectric can be between the first and second electrodes, the first electrode and the capacitor dielectric can be between the second electrode and the substrate, and the first and second electrodes and the capacitor dielectric can be between the hard mask and the substrate. An interlayer dielectric layer can be formed on the hard mask and on portions of the substrate surrounding the capacitor structure, and portions of the interlayer dielectric layer can be removed to expose the hard mask while maintaining portions of the interlayer dielectric layer on portions of the substrate surrounding the capacitor structure. The hard mask can then be removed thereby exposing portions of the second electrode while maintaining the portions of the interlayer dielectric layer on portions of the substrate surrounding the capacitor.

Abstract translation: 用于形成电子器件的方法可以包括在衬底的一部分上形成电容器结构，其中电容器结构包括衬底上的第一电极，第一电极上的电容器电介质，电介质上的第二电极以及开口上的硬掩模 第二电极。 更具体地，电容器电介质可以在第一和第二电极之间，第一电极和电容器电介质可以在第二电极和基板之间，并且第一和第二电极以及电容器电介质可以在硬掩模和电容器电介质之间 基质。 可以在硬掩模上以及围绕电容器结构的衬底的部分上形成层间电介质层，并且层间电介质层的部分可以被去除以暴露硬掩模，同时保持部分衬底上的层间电介质层的部分 围绕电容器结构。 然后可以移除硬掩模，由此暴露第二电极的部分，同时将衬底的围绕电容器的部分衬底上的层间介电层的部分保持。

公开(公告)号：KR1020040072220A

公开(公告)日：2004-08-18

申请号：KR1020030008202

申请日：2003-02-10

Applicant: 삼성전자주식회사

Inventor： 송윤종 ,  김기남 ,  장낙원

IPC: H01L27/105

CPC classification number: H01L27/11502 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/65

Abstract: PURPOSE: A ferroelectric memory device and a fabricating method thereof are provided to enhance an electrical characteristic by restricting the undesired reaction between a ferroelectric and an interlayer dielectric. CONSTITUTION: A transistor is formed on a semiconductor substrate(100). The first interlayer dielectric(116b) is formed on the semiconductor substrate. A bit line(120) is partially on the first interlayer dielectric. The second interlayer dielectric(122a) is formed on the entire surface of the first interlayer dielectric. A buried plug(126) penetrates the second interlayer dielectric and the first interlayer dielectric. A buried capacitor bottom electrode(134) is electrically connected to the buried plug. The third interlayer dielectric(138a) is formed between the buried capacitor bottom electrodes. A reactive buffer layer(140) is formed on the third interlayer dielectric. A capacitor ferroelectric layer(142) is formed between the buried capacitor bottom electrode and the reactive buffer layer. A capacitor top electrode(148) is formed on the capacitor ferroelectric layer.

Abstract translation: 目的：提供铁电存储器件及其制造方法，以通过限制铁电体和层间电介质之间的不期望的反应来增强电特性。 构成：晶体管形成在半导体衬底（100）上。 第一层间电介质（116b）形成在半导体衬底上。 位线（120）部分地位于第一层间电介质上。 第二层间电介质（122a）形成在第一层间电介质的整个表面上。 埋入式插塞（126）穿透第二层间电介质和第一层间电介质。 掩埋电容器底部电极（134）电连接到埋置的插塞。 第三层间电介质（138a）形成在埋入的电容器底部电极之间。 在第三层间电介质上形成反应缓冲层（140）。 在埋入式电容器底部电极和反应性缓冲层之间形成电容器铁电层142。 电容器顶电极（148）形成在电容器铁电层上。

公开(公告)号：KR1020040034825A

公开(公告)日：2004-04-29

申请号：KR1020020063443

申请日：2002-10-17

Applicant: 삼성전자주식회사

Inventor： 최문규 ,  민병준 ,  전병길 ,  김기남

IPC: G11C11/22

CPC classification number: G11C7/22 ,  G11C2207/2281 ,  G11C2207/229

Abstract: PURPOSE: A ferroelectric memory device and its control method are provided to perform an asynchronous operation by using an address transition detection method. CONSTITUTION: According to a nonvolatile semiconductor memory device including a memory cell array(210) having nonvolatile memory cells arranged in a row and column in a matrix, a pulse generator circuit(290) generates a pulse signal in response to transition of an address. A chip enable buffer circuit(300) enables a chip enable flag signal in response to the first transition of the pulse signal. A row selection circuit(220) selects one of the rows and drives it in response to the address during the enabling of the chip enable flag signal, and generates a flag signal informing the selection of a plate line. And a control circuit(310) enables a plate control signal in response to the enabling of a write enable signal, and disables the plate control signal in response to the second transition of the pulse signal.

Abstract translation: 目的：提供铁电存储器件及其控制方法，通过使用地址转换检测方法来执行异步操作。 构成：根据具有以矩阵形式排列成行和列的非易失性存储单元的存储单元阵列（210）的非易失性半导体存储器件，脉冲发生电路（290）响应于地址的转换而产生脉冲信号。 芯片使能缓冲器电路（300）响应于脉冲信号的第一转换而启用芯片使能标志信号。 行选择电路（220）在芯片使能标志信号的使能期间响应于地址选择行中的一个并驱动它，并且产生通知板线选择的标志信号。 并且控制电路（310）响应于使能写使能信号而启用板控制信号，并且响应于脉冲信号的第二转换而禁用板控制信号。

公开(公告)号：KR1020040022566A

公开(公告)日：2004-03-16

申请号：KR1020020054169

申请日：2002-09-09

Applicant: 삼성전자주식회사

Inventor： 최문규 ,  전병길 ,  김기남

IPC: G11C5/06

CPC classification number: G11C11/405 ,  G11C11/404

Abstract: PURPOSE: A memory device including memory cells having complementary data is provided to reduce the number of sense amplifiers and the power consumption by arranging a memory cell between a couple of memory cells and a complementary memory cell and connecting selectively the selected memory cell and the complementary memory cell to the sense amplifier. CONSTITUTION: A memory device including memory cells having complementary data includes a memory cell array block(610), the first sense amplifier(640), the second sense amplifier(650), the first switch(620), and the second switch(630). The memory cell array block(610) includes the first to the fourth memory cells and the first to the fourth complementary memory cells. The first sense amplifier(640) is arranged at a top end part of the memory cell array block. The second sense amplifier(650) is arranged at the end of the memory cell array block. The first switch(620) is used for connecting the first sense amplifier to bit lines between the first memory cell and the complementary memory cells or connecting the second sense amplifier to the bit lines between the second memory cell and the complementary memory cells. The second switch(630) is used for connecting the first sense amplifier to bit lines between the third memory cell and the complementary memory cells or connecting the second sense amplifier to the bit lines between the fourth memory cell and the complementary memory cells.

Abstract translation: 目的：提供包括具有互补数据的存储单元的存储器件，以通过将存储单元布置在一对存储单元和互补存储单元之间来选择性地连接选定的存储单元和互补的存储单元，以减少读出放大器的数量和功耗 存储单元到读出放大器。 构成：包括具有互补数据的存储单元的存储器件包括存储单元阵列块（610），第一读出放大器（640），第二读出放大器（650），第一开关（620）和第二开关（630） ）。 存储单元阵列块（610）包括第一至第四存储器单元和第一至第四互补存储器单元。 第一读出放大器（640）布置在存储单元阵列块的顶端部分。 第二读出放大器（650）布置在存储单元阵列块的末端。 第一开关（620）用于将第一读出放大器连接到第一存储单元和互补存储单元之间的位线，或者将第二读出放大器连接到第二存储单元和互补存储单元之间的位线。 第二开关（630）用于将第一读出放大器连接到第三存储单元和互补存储单元之间的位线，或者将第二读出放大器连接到第四存储单元和互补存储单元之间的位线。

公开(公告)号：KR100416591B1

公开(公告)日：2004-02-05

申请号：KR1020010004222

申请日：2001-01-30

Applicant: 삼성전자주식회사

Inventor： 정홍식 ,  양원석 ,  김기남

IPC: H01L27/10

CPC classification number: H01L27/10894 ,  H01L27/10855

Abstract: An etch-stop layer (68) is selectively provided between layers of a multiple-layered circuit so as to allow for outgassing of impurities during subsequent fabrication processes. The etch-stop layer is formed over an underlying stud (62B) so as to serve as an alignment target during formation of an overlying stud (74) formed in an upper layer to be coupled to the underlying stud (62B). In this manner multiple-layered circuits, for example memory devices, can be fabricated in relatively dense configurations.

Abstract translation: 在多层电路的层之间选择性地提供蚀刻停止层（68），以允许在随后的制造工艺期间杂质的除气。 蚀刻停止层形成在下面的双头螺栓（62B）上方，以便在形成上层螺栓（74）的上层螺柱（74）形成过程中用作对准目标，以与下面的双头螺栓（62B）耦合。 以这种方式，可以以相对密集的配置来制造多层电路，例如存储器设备。 ＆lt;图像＆GT;

公开(公告)号：KR1020030096463A

公开(公告)日：2003-12-31

申请号：KR1020020032974

申请日：2002-06-12

Applicant: 삼성전자주식회사

Inventor： 김지영 ,  김기남

IPC: H01L27/092

CPC classification number: H01L21/823412 ,  H01L21/761 ,  H01L21/823425 ,  H01L21/823481 ,  H01L21/823878 ,  H01L29/0649 ,  H01L29/66651 ,  H01L29/78

Abstract: PURPOSE: A semiconductor device and a method for manufacturing the same are provided to be capable of effectively preventing the generation of junction short between a source and a drain at a bulk area for improving the electrical characteristic of an MOS(Metal Oxide Semiconductor) transistor. CONSTITUTION: A semiconductor device is provided with a semiconductor substrate(100), an isolation layer(110) formed at the semiconductor substrate, a gate(150) selectively formed at the upper portion of the resultant structure, and a source and drain junction(105) formed at both sides of the gate at the inner portion of the semiconductor substrate. The semiconductor device further includes a channel silicon layer located at the lower portion of a gate isolating layer of the gate for connecting the source junction with the drain junction and a buried insulating layer(125) made of a silicon insulating layer, located at the lower portion of the channel silicon layer for blocking between the source and drain junction.

Abstract translation: 目的：提供一种半导体器件及其制造方法，以能够有效地防止在体积区域产生源极和漏极之间的结短，从而改善MOS（金属氧化物半导体）晶体管的电特性。 构成：半导体器件设置有半导体衬底（100），形成在半导体衬底处的隔离层（110），选择性地形成在所得结构的上部的栅极（150）以及源极和漏极结（ 105），形成在半导体衬底的内部的栅极的两侧。 所述半导体器件还包括位于所述栅极的栅极隔离层的下部的沟道硅层，用于将所述源极结与所述漏极结连接，以及由位于下部的硅绝缘层制成的掩埋绝缘层（125） 用于在源极和漏极结之间阻塞的沟道硅层的一部分。

公开(公告)号：KR100395765B1

公开(公告)日：2003-08-25

申请号：KR1020010005147

申请日：2001-02-02

Applicant: 삼성전자주식회사

Inventor： 김현호 ,  김기남

IPC: H01L27/105

CPC classification number: H01L27/11502 ,  H01L23/522 ,  H01L27/11507 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuit ferroelectric memory devices are provided that include an integrated circuit transistor. The memory device further includes a ferroelectric capacitor on the integrated circuit transistor. The ferroelectric capacitor includes a first electrode adjacent the transistor, a second electrode remote from the transistor and a ferroelectric film therebetween. The memory device further includes a plate line directly on the ferroelectric capacitor. Methods are also provided that include forming a ferroelectric capacitor on the integrated circuit transistor and forming a plate line directly on the ferroelectric capacitor.

Abstract translation: 提供集成电路铁电存储器器件，其包括集成电路晶体管。 存储器件还包括集成电路晶体管上的铁电电容器。 铁电电容器包括与晶体管相邻的第一电极，远离晶体管的第二电极和位于其间的铁电薄膜。 存储器件还包括直接位于铁电电容器上的板线。 还提供了方法，包括在集成电路晶体管上形成铁电电容器并直接在铁电电容器上形成板线。

公开(公告)号：KR100393222B1

公开(公告)日：2003-07-31

申请号：KR1020010022677

申请日：2001-04-26

Applicant: 삼성전자주식회사

Inventor： 장세명 ,  김기남 ,  정홍식 ,  황유상

IPC: H01L27/108

CPC classification number: H01L27/10855 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/10814 ,  H01L28/91

Abstract: A semiconductor device including storage nodes of a capacitor and a method for manufacturing the same are provided. Bit lines are formed on a semiconductor substrate, and protection layers are formed to cover and protect the bit lines. Conductive contact pads are formed between the bit lines and are level with the top surfaces of the protection layers. A node supporting layer is formed to cover the conductive contact pads and the protection layers. An etching stopper is formed on the node supporting layer. The mold layer, the etching stopper, and the node supporting layer are patterned, thereby forming opening holes exposing the conductive pads. Storage nodes are formed in the opening holes and have the shape of the profile of the opening holes. The mold layer exposed by the storage nodes is removed, thereby exposing the outer wall of each of the storage nodes positioned above the etching stopper.

Abstract translation: 提供了一种包括电容器的存储节点的半导体器件及其制造方法。 位线形成在半导体衬底上，并形成保护层以覆盖和保护位线。 导电接触垫形成在位线之间并且与保护层的顶面齐平。 形成节点支撑层以覆盖导电接触垫和保护层。 蚀刻停止层形成在节点支撑层上。 模制层，蚀刻停止层和节点支撑层被图案化，由此形成暴露导电焊盘的开孔。 存储节点形成在开孔中并且具有开孔的轮廓形状。 由存储节点暴露的模制层被去除，由此暴露位于蚀刻阻挡层上方的每个存储节点的外壁。

公开(公告)号：KR100389925B1

公开(公告)日：2003-07-04

申请号：KR1020010011156

申请日：2001-03-05

Applicant: 삼성전자주식회사

Inventor： 양원석 ,  송상호 ,  김기남 ,  정홍식

IPC: H01L27/108

CPC classification number: H01L27/10894 ,  H01L21/76895 ,  H01L23/485 ,  H01L27/10882 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A conductive portion connects a lower conductive layer formed on a semiconductor substrate provided in a first interlayer insulating layer to an upper conductive layer formed on the lower conductive layer, and provided in a second interlayer insulating layer. This portion is divided into at least one plug and a pad. At least one plug is formed in a first interlayer insulating layer and the lower part of a second interlayer insulating layer. The second interlayer insulating layer is divided into a plurality of interlayer insulating layers so that upper and lower widths of the divided plugs formed in the divided portion of the second interlayer insulating layer are not greatly different from each other. The pad formed on the upper portion of the second interlayer insulating layer has an upper width such that the upper conductive layer connected to the pad is not undesirably connected to an adjacent upper conductive layer via the pad.

Abstract translation: 导电部分将形成在设置在第一层间绝缘层中的半导体衬底上的下导电层连接到形成在下导电层上的上导电层，并且设置在第二层间绝缘层中。 这部分被分成至少一个插头和一个垫。 在第一层间绝缘层和第二层间绝缘层的下部中形成至少一个插塞。 第二层间绝缘层被分成多个层间绝缘层，使得在第二层间绝缘层的分割部分中形成的分割插塞的上下宽度彼此没有很大不同。 形成在第二层间绝缘层的上部上的焊盘具有上部宽度，使得连接到焊盘的上部导电层不会不希望地经由焊盘连接到相邻的上部导电层。