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公开(公告)号：KR1020120035064A
公开(公告)日：2012-04-13
申请号：KR1020100096550
申请日：2010-10-04
Applicant: 삼성전자주식회사
CPC classification number: G11C16/02 , G06F13/00 , G11C11/5642 , G11C16/00 , G11C16/06 , G11C16/3418 , G11C16/349 , G11C29/42
Abstract: PURPOSE: An apparatus and method for changing a read parameter are provided to reduce an ECC decoding failure by previously changing a lead parameter after a read operation or an ECC decoding of read data is successful. CONSTITUTION: A first data saved in a memory cell array(22) is read by using a read voltage. The read voltage is changed to read a second data saved in a first region of the memory cell array according to a comparison result of a count value of 0 and 1 included in the first data and a reference count value. The changed read voltage information is saved in a second region of the memory cell array. A second data is read by using the changed read voltage corresponding to the information saved in a second region.
Abstract translation: 目的：提供一种用于改变读取参数的装置和方法，用于通过在读取操作之后先前改变引导参数或读取数据的ECC解码成功来减少ECC解码失败。 构成：通过使用读取电压读取保存在存储单元阵列（22）中的第一数据。 根据第一数据中包含的计数值0和1的比较结果和参考计数值，改变读取电压以读取保存在存储单元阵列的第一区域中的第二数据。 改变的读取电压信息被保存在存储单元阵列的第二区域中。 通过使用与保存在第二区域中的信息相对应的改变的读取电压来读取第二数据。
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公开(公告)号：KR1020100127406A
公开(公告)日：2010-12-06
申请号：KR1020090045838
申请日：2009-05-26
Applicant: 삼성전자주식회사
CPC classification number: G11C16/26 , G06F11/1048 , G11C11/5642 , G11C16/0483 , G11C29/00
Abstract: PURPOSE: A storing apparatus and a reading method of the same are provided to optimize a reading operation by setting a reading level based on a filtered distribution of the reading operation. CONSTITUTION: A storing unit(12) stores data. An error controlling unit(14) corrects the errors of data read from the strong unit based on at least one reading level. The error controlling unit outputs a error correcting failure signal(ECF). A reading level controlling unit(16) responds to the error correcting failure signal and sets a new reading level. The reading level controlling unit includes a filter(17) in order to filter the measured distribution of memory cells from the storing unit.
Abstract translation: 目的：提供存储装置及其读取方法，以通过基于读取操作的滤波分布设置读取级别来优化读取操作。 构成：存储单元（12）存储数据。 错误控制单元（14）基于至少一个读取级别来校正从强单元读取的数据的错误。 误差控制单元输出纠错失败信号（ECF）。 读取电平控制单元（16）响应纠错失败信号并设置新的读取电平。 读取电平控制单元包括滤波器（17），以便从存储单元滤出测量的存储单元分布。
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公开(公告)号：KR1020100124892A
公开(公告)日：2010-11-30
申请号：KR1020090043825
申请日：2009-05-20
Applicant: 삼성전자주식회사
CPC classification number: G11C11/5642 , G11C29/00 , G11C2211/5634 , G11C16/26
Abstract: PURPOSE: A method for setting a read voltage is provided to minimize the number of a bit in which an error is generated by compensating an offset. CONSTITUTION: A first voltage distribution corresponds to a first voltage-state. A second voltage distribution corresponds to a second voltage state. A read error probability value use a read voltage as a variable. The read error probability value is calculated based on the first and second voltage distribution and control the read voltage to be minimum.
Abstract translation: 目的：提供一种用于设置读取电压的方法，以通过补偿偏移来最小化产生错误的位的数量。 构成：第一电压分布对应于第一电压状态。 第二电压分布对应于第二电压状态。 读错误概率值使用读取电压作为变量。 基于第一和第二电压分布计算读误差概率值，并将读电压控制为最小。
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公开(公告)号：KR1020100088898A
公开(公告)日：2010-08-11
申请号：KR1020090008039
申请日：2009-02-02
Applicant: 삼성전자주식회사
CPC classification number: G11C16/3418 , G11C11/5621 , G11C16/12 , G11C16/3436
Abstract: PURPOSE: A flash memory device, a program thereof, and a reading method thereof are provided to control a program voltage of memory cells adjacent to the memory cell of an erase state by using a control logic unit. CONSTITUTION: A memory cell array(110) comprises a plurality of memory cells. Memory cells are connected between corresponding word lines and bit lines. The memory cells has an erase sate and first to (N-1)-th program states. A state detector(180) detects the memory cell of the erase state among the memory cells. A control logic unit(160) controls the program voltage about the memory cells adjacent to the memory cells of the erase state according to the detection result of the state detector. The control logic unit performs the program different from the first to (N-1)-th programs.
Abstract translation: 目的：提供闪速存储器件，其程序及其读取方法，以通过使用控制逻辑单元来控制与擦除状态的存储单元相邻的存储单元的编程电压。 构成：存储单元阵列（110）包括多个存储单元。 存储单元连接在相应的字线和位线之间。 存储单元具有擦除状态和第一到第（N-1）个程序状态。 状态检测器（180）检测存储单元中的擦除状态的存储单元。 根据状态检测器的检测结果，控制逻辑单元（160）控制与擦除状态的存储单元相邻的存储单元的编程电压。 控制逻辑单元执行与第一至第（N-1）个程序不同的程序。
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公开(公告)号：KR1020100067942A
公开(公告)日：2010-06-22
申请号：KR1020080126551
申请日：2008-12-12
Applicant: 삼성전자주식회사
CPC classification number: G11C16/3427 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/3418 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5634 , G11C16/34 , G11C16/10
Abstract: PURPOSE: An access method of a non-volatile memory device is provided to supply a reliable data by calculating the size of the physical effect which a sacrifice cell receives referring to the data states. CONSTITUTION: A threshold voltage of a second memory cell interfering with the change of a second memory cell is detected(S10). The threshold voltage of a first and a second memory cell is distinguished into one of a plurality of sub-distributions according to the change of the threshold voltage of the cell(S20). The first memory cell is read out by a reading voltage to distinguish one sub-distribution from a plurality of sub-distribution(S30). The reading voltage of a first memory cell is read out by referring to sub-distribution according to the number of page which is programmed in the first memory cell(S40).
Abstract translation: 目的：提供非易失性存储器件的访问方法，通过计算牺牲单元接收到的数据状态的物理效应的大小来提供可靠数据。 构成：检测到干扰第二存储单元的变化的第二存储单元的阈值电压（S10）。 根据单元的阈值电压的变化，将第一和第二存储单元的阈值电压区分为多个子分布中的一个（S20）。 通过读取电压读出第一存储单元，以区分一个子分布与多个子分布（S30）。 通过参照在第一存储器单元中编程的页面数量的子分布来读出第一存储单元的读取电压（S40）。
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Patent Agency Ranking
公开(公告)号：KR1020090117172A
公开(公告)日：2009-11-12
申请号：KR1020080043087
申请日：2008-05-08
Applicant: 삼성전자주식회사
CPC classification number: G11C16/26 , G06F11/1068 , G06F11/1072 , G11C11/5642 , G11C16/30
Abstract: PURPOSE: A memory device and a memory data reading method for MLC and MBC are provided to reduce time for search reading voltage level and read from the memory device by using writing voltage level. CONSTITUTION: A memory device(100) includes a memory cell array(110), a reading unit(120), and a controller(130). The memory cell array includes memory cells. The reading unit reads data from the memory cell array and uses the first reading voltage level. The reading unit produces the first index information based on data. The controller reads the second index information stored in the memory cell array.
Abstract translation: 目的：提供用于MLC和MBC的存储器件和存储器数据读取方法，以减少搜索读取电压电平的时间并通过使用写入电压电平从存储器件读取。 构成：存储器件（100）包括存储单元阵列（110），读取单元（120）和控制器（130）。 存储单元阵列包括存储单元。 读取单元从存储单元阵列读取数据并使用第一读取电压电平。 读取单元基于数据产生第一索引信息。 控制器读取存储在存储单元阵列中的第二索引信息。
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公开(公告)号：KR1020080077795A
公开(公告)日：2008-08-26
申请号：KR1020070017444
申请日：2007-02-21
Applicant: 삼성전자주식회사
IPC: H03M1/12
CPC classification number: H03M1/361 , H03M1/002 , H03M1/368 , H03M2201/2208 , H03M2201/52
Abstract: An analog/digital converter using a multiplexer and a conversion method thereof are provided to convert an analog signal into binary codes without a process for conversion to 1-of-n codes by installing the multiplexer, having a simple structure, in an encoder. An analog/digital converter using a multiplexer includes a digital code generation unit(300) and a binary code generation unit(500). The digital code generation unit compares an analog input signal with reference voltages of each level, and then generates a plurality of digital codes. The binary code generation unit has a plurality of multiplexers corresponding to the number of the generated digital codes and generates binary codes by switching the digital codes by using the multiplexers.
Abstract translation: 提供了一种使用多路复用器的模/数转换器及其转换方法，用于将模拟信号转换为二进制码，而无需通过在编码器中安装具有简单结构的多路复用器将其转换为1-n码的处理。 使用复用器的模拟/数字转换器包括数字代码生成单元（300）和二进制代码生成单元（500）。 数字代码生成单元将模拟输入信号与各级的参考电压进行比较，然后生成多个数字代码。 二进制代码生成单元具有与生成的数字代码的数量对应的多个复用器，并且通过使用多路复用器切换数字代码来生成二进制代码。
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公开(公告)号：KR100787214B1
公开(公告)日：2007-12-21
申请号：KR1020050078165
申请日：2005-08-25
Applicant: 삼성전자주식회사
IPC: H03M13/41
CPC classification number: H03M13/413 , H03M13/6597
Abstract: 본 발명은 아날로그 비터비 디코더에 관한 것이다. 본 발명에 따른 아날로그 비터비 디코더는 트렐리스 다이어그램 상의 각 노드에 대응되도록 세로로 배열된 복수 개의 셀로 구성된 처리단을 복수 개 구비하며, 복수 개의 처리단 중 최종단이 최초단과 연결되는 순환형 연결구조를 가지는 아날로그신호처리셀을 이용하여 아날로그 입력 데이터를 디코딩하는 디코딩부와, 디코딩부에 구비된 복수 개의 처리단에 병렬적으로 연결된 복수 개의 콘덴서를 포함하는 아날로그데이터저장부와, 외부로부터 입력되는 아날로그 데이터를 샘플링하여 출력하는 복수 개의 샘플앤홀드부를 병렬로 구비하고, 복수 개의 샘플앤홀드부에서 각각 샘플링된 아날로그 데이터를 순차교번하여 출력하는 아날로그신호입력부와, 아날로그신호입력부에서 출력되는 아날로그 데이터를 아날로그데이터저장부 중 소정 콘덴서에 저장하는 제1스위치부 및, 외부로부터 입력된 제1 클럭신호에 따라 디코딩부에 구비된 복수 개의 처리단을 순차적으로 지정하고, 제1스위치부를 제어하여 아날로그신호입력부에서 출력되는 아날로그 데이터를 아날로그데이터저장부의 특정 콘덴서에 순차적으로 저장하는 작업을 수행하는 제어부를 포함한다.
비터비, 디코더, 샘플앤홀드, 병렬, 아날로그 -
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