-
公开(公告)号：KR100389925B1
公开(公告)日：2003-07-04
申请号：KR1020010011156
申请日：2001-03-05
Applicant: 삼성전자주식회사
IPC: H01L27/108
CPC classification number: H01L27/10894 , H01L21/76895 , H01L23/485 , H01L27/10882 , H01L2924/0002 , H01L2924/00
Abstract: A conductive portion connects a lower conductive layer formed on a semiconductor substrate provided in a first interlayer insulating layer to an upper conductive layer formed on the lower conductive layer, and provided in a second interlayer insulating layer. This portion is divided into at least one plug and a pad. At least one plug is formed in a first interlayer insulating layer and the lower part of a second interlayer insulating layer. The second interlayer insulating layer is divided into a plurality of interlayer insulating layers so that upper and lower widths of the divided plugs formed in the divided portion of the second interlayer insulating layer are not greatly different from each other. The pad formed on the upper portion of the second interlayer insulating layer has an upper width such that the upper conductive layer connected to the pad is not undesirably connected to an adjacent upper conductive layer via the pad.
Abstract translation: 导电部分将形成在设置在第一层间绝缘层中的半导体衬底上的下导电层连接到形成在下导电层上的上导电层，并且设置在第二层间绝缘层中。 这部分被分成至少一个插头和一个垫。 在第一层间绝缘层和第二层间绝缘层的下部中形成至少一个插塞。 第二层间绝缘层被分成多个层间绝缘层，使得在第二层间绝缘层的分割部分中形成的分割插塞的上下宽度彼此没有很大不同。 形成在第二层间绝缘层的上部上的焊盘具有上部宽度，使得连接到焊盘的上部导电层不会不希望地经由焊盘连接到相邻的上部导电层。
-
62.发明授权
公开(公告)号：KR100385954B1
公开(公告)日：2003-06-02
申请号：KR1020010004223
申请日：2001-01-30
Applicant: 삼성전자주식회사
IPC: H01L27/10
CPC classification number: H01L21/76897 , H01L21/76829 , H01L21/76834 , H01L27/10882 , H01L27/10894
Abstract: An etch-stop layer is selectively provided between layers of a multiple-layered circuit in a selective manner so as to allow for outgassing of impurities during subsequent fabrication processes. The etch-stop layer is formed over an underlying stud so as to serve as an alignment target during formation of an overlying stud formed in an upper layer. In this manner multiple-layered circuits, for example memory devices, can be fabricated in relatively dense configurations.
Abstract translation: 蚀刻停止层以选择性的方式选择性地设置在多层电路的层之间，以允许在随后的制造工艺期间杂质的除气。 蚀刻停止层形成在下面的柱上，以便在上层中形成的上面的柱中形成对准目标。 以这种方式，可以以相对密集的配置来制造多层电路，例如存储器设备。
-
公开(公告)号：KR1020020066670A
公开(公告)日：2002-08-21
申请号：KR1020010006985
申请日：2001-02-13
Applicant: 삼성전자주식회사
IPC: H01L21/308
CPC classification number: H01L21/31144 , H01L21/31138 , H01L21/316 , H01L21/76802 , H01L21/76814 , H01L21/76826 , H01L21/76828 , H01L21/76829
Abstract: PURPOSE: A patterning method of an SOG(Spin On Glass) is provided to prevent a bad profile of an SOG pattern due to a cleaning process by performing a two-step curing. CONSTITUTION: An SOG(102a) is deposited on a semiconductor substrate formed with defined patterns. The first curing is performed on the SOG(102a) at the temperature of 600-800 deg.C in an H2O gas or an O2 gas condition. A hard mask pattern(104) is formed on the SOG(102a). Then, the SOG(102a) is selectively etched by using the hard mask pattern(104) as a mask. The second curing is performed on the etched SOG(102a) at the temperature of 400-800 deg.C in the same gas condition with the first curing. Then, remaining SOG(102a) is removed by etching using the hard mask pattern(104) as a mask.
Abstract translation: 目的：提供SOG（旋转玻璃）的图案化方法，以通过进行两步固化来防止由于清洁处理而导致的SOG图案的不良轮廓。 构成：将SOG（102a）沉积在形成有限定图案的半导体衬底上。 在H 2 O气体或O 2气体条件下，在600-800℃的温度下，在SOG（102a）上进行第一次固化。 在SOG（102a）上形成硬掩模图案（104）。 然后，通过使用硬掩模图案（104）作为掩模来选择性地蚀刻SOG（102a）。 在与第一次固化相同的气体条件下，在400-800℃的温度下，对蚀刻的SOG（102a）进行第二次固化。 然后，使用硬掩模图案（104）作为掩模通过蚀刻去除剩余的SOG（102a）。
-
公开(公告)号：KR1020020065983A
公开(公告)日：2002-08-14
申请号：KR1020010006123
申请日：2001-02-08
Applicant: 삼성전자주식회사
IPC: H01L21/28
CPC classification number: H01L23/485 , H01L21/76801 , H01L21/76804 , H01L21/76877 , H01L21/76895 , H01L23/5226 , H01L2924/0002 , H01L2924/00
Abstract: PURPOSE: A semiconductor device having a multi-layered interconnection structure is provided to prevent a short-circuit between a landing pad and a circuit pattern, by forming a step-type contact stud, by forming a pillar-type contact stud in an interlayer dielectric and by forming a conductive pattern for a landing pad on the interlayer dielectric such that the conductive pattern is of a size greater than the line width of the contact stud. CONSTITUTION: The interlayer dielectric is formed on a semiconductor substrate(200). The first contact stud is formed in the interlayer dielectric, in which the line width of an inlet part adjacent to the surface of the interlayer dielectric is greater than that of a contact part adjacent to the substrate. The second stud is formed in the interlayer dielectric, separated from the first contact stud by a predetermined interval.
Abstract translation: 目的：提供具有多层互连结构的半导体器件，以通过在层间电介质中形成柱状接触柱来形成台阶式接触柱，以防止接地焊盘和电路图案之间的短路 并且通过在层间电介质上形成用于着陆焊盘的导电图案，使得导电图案的尺寸大于接触柱的线宽度。 构成：层间电介质形成在半导体衬底（200）上。 第一接触柱形成在层间电介质中，其中与层间电介质的表面相邻的入口部分的线宽大于与衬底相邻的接触部分的线宽。 第二螺柱形成在层间电介质中，以预定的间隔与第一接触柱分开。
-
65.发明公开식각 저지층이 구비된 비트 라인 스터드 상에 비트 라인랜딩 패드와 비경계 콘택을 갖는 반도체 소자 및 그형성방법 有权具有隔离层的双面线路板上的位线接线和无边界接触的半导体器件及其制造方法
公开(公告)号：KR1020020033484A
公开(公告)日：2002-05-07
申请号：KR1020010004222
申请日：2001-01-30
Applicant: 삼성전자주식회사
IPC: H01L27/10
CPC classification number: H01L27/10894 , H01L27/10855
Abstract: PURPOSE: A semiconductor device having a bit line landing pad and a borderless contact on a bit line stud having an etch stop layer is provided to guarantee precision of an etch depth, by forming the etch stop layer on the stud of a lower layer such that the etch stop layer has etch selectively different from that of a lower insulation layer. CONSTITUTION: The first stud is formed in the first insulation layer(58). The etch stop layer(68) is formed on the first stud. The second insulation layer is formed on the etch stop layer. The second stud passes through the second insulation layer and the etch stop layer, electrically connected to the first stud. The etch stop layer has a different etch selectivity from that of the second insulation layer.
Abstract translation: 目的：提供具有位线着陆焊盘和位于具有蚀刻停止层的位线螺柱上的无边界触点的半导体器件，以通过在较低层的螺柱上形成蚀刻停止层来确保蚀刻深度的精度，使得 蚀刻停止层具有与下绝缘层的蚀刻选择性不同的蚀刻。 构成：第一螺柱形成在第一绝缘层（58）中。 蚀刻停止层（68）形成在第一螺柱上。 第二绝缘层形成在蚀刻停止层上。 第二螺柱穿过电连接到第一螺柱的第二绝缘层和蚀刻停止层。 蚀刻停止层具有与第二绝缘层的蚀刻选择性不同的蚀刻选择性。
-
Patent Agency Ranking
公开(公告)号：KR1020010036018A
公开(公告)日：2001-05-07
申请号：KR1019990042852
申请日：1999-10-05
Applicant: 삼성전자주식회사
IPC: H01L27/108
Abstract: PURPOSE: A method for manufacturing a bitline contact of a semiconductor device is provided to form stable metal silicide layers in different regions, by forming a silicon supply layer inside a contact hole before a metal layer for forming the silicide layer is manufactured. CONSTITUTION: A plurality of the first and second transistors having at least a gate electrode(120,140) composed of polysilicon/tungsten silicide are formed on a semiconductor substrate(100) in which a cell array region and a peripheral region are defined. The first interlayer dielectric(220) is formed on the substrate including the plurality of the first and second transistors. A conductive pad is formed among the plurality of the first transistors. The second interlayer dielectric(260) is formed on the first interlayer dielectric, the conductive pad and the first and second transistors. The second interlayer dielectric is etched to form the first, second and third bitline contact holes(280a,280b,280c) exposing the conductive pad, the substrate on both sides of the second transistors and the tungsten silicide layer, respectively. A silicon supply layer(300) is formed in the second interlayer dielectric and the bitline contact hole. A metal layer(320) for forming silicide is deposited and annealed on the silicon supply layer to form a metal silicide layer. A barrier metal layer is formed on the silicide layer. A bitline metal layer is formed on the barrier metal layer.
Abstract translation: 目的：提供一种用于制造半导体器件的位线接触的方法，以在制造用于形成硅化物层的金属层之前在接触孔内形成硅供应层，以在不同区域中形成稳定的金属硅化物层。 构成：在其中限定了电池阵列区域和外围区域的半导体衬底（100）上形成至少具有由多晶硅/硅化钨构成的栅电极（120,140）的多个第一和第二晶体管。 在包括多个第一和第二晶体管的基板上形成第一层间电介质（220）。 在多个第一晶体管中形成导电焊盘。 第二层间电介质（260）形成在第一层间电介质，导电焊盘和第一和第二晶体管上。 蚀刻第二层间电介质以形成分别暴露导电焊盘，第二晶体管两侧的衬底和硅化钨层的第一，第二和第三位线接触孔（280a，280b，280c）。 在第二层间电介质和位线接触孔中形成硅供给层（300）。 用于形成硅化物的金属层（320）在硅供应层上沉积并退火以形成金属硅化物层。 在硅化物层上形成阻挡金属层。 在阻挡金属层上形成位线金属层。
-
公开(公告)号：KR1019980008899A
公开(公告)日：1998-04-30
申请号：KR1019960031157
申请日：1996-07-29
Applicant: 삼성전자주식회사
IPC: H01L21/306
-
公开(公告)号：KR1019970077300A
公开(公告)日：1997-12-12
申请号：KR1019960018234
申请日：1996-05-28
Applicant: 삼성전자주식회사
IPC: H01L21/304
Abstract: 본 발명은 반도체 제조용 건식 식각 장치에 관한 것으로, 본 발명에 따른 건식 식각 장치는 식각 챔버로의 공급 가스의 유량을 제어하는 MFC와, 상기 식각 챔버 내의 플라즈마로부터 방출되는 빛을 접속시켜서 광 화이버에 전달시키는 렌즈 시스템과, 상기 광 화이버를 통해 조사(照射)된 빛의 스펙트럼을 발생시키는 광 다이오드 어레이를 포함하는 분광기와, 상기 광 다이오드 어레이에서 발생된 스펙트럼을 기초로 하여 상기 MFC의 작동을 제어하는 제어장치를 포함한다. 본 발명에 의하면, 반도체 제조용 건식 식각 장치에서 식각 챔버 내의 잔류 가스에 의한 분위기 변화를 감소시킬 수 있다.
-
公开(公告)号：KR1019970008354A
公开(公告)日：1997-02-24
申请号：KR1019950023171
申请日：1995-07-31
Applicant: 삼성전자주식회사
IPC: H01L21/28
Abstract: 폴리머를 이용한 작은 콘택홀을 갖는 반도체 장치의 제조방법에 관하여 개시한다. 본 발명은 반도체 기판상에 패터닝하고자 하는 소정의 층을 형성하는 단계와, 상기 소정의 층 상에 제1콘택홀을 갖는 포토레지스트 패턴을 형성하는 단계와, 상기 포토레지스트 패턴이 형성된 기판의 전면에 상기 포토레지스트 패턴의 소모없이 폴리머층을 형성하는 단계와, 상기 폴리머층을 건식식각하여 상기 포토레지스트 패턴을 측벽에 스페이서를 형성한 후, 상기 포토레지스트 패턴 및 스페이서를 마스크로 상기 소정의 층을 건식식각하여 상기 제1콘택홀보다 작은 제2콘택홀을 형성하는 단계를 포함한다. 본 발명에 의하면, 폴리머층을 이용하여 사진공정의 한계해상도 이하의 스몰 콘택홀을 형성할 수 있다.
-
-
-
-
-
-
-
-
-
Search Results
71
records
(took 0.027 seconds)
