公开(公告)号：KR200058010Y1

公开(公告)日：1991-07-24

申请号：KR2019880022170

申请日：1988-12-30

Applicant: 한국전자통신연구원 ,  주식회사 케이티

Inventor： 문하연 ,  강봉수 ,  박성호

IPC: H05B6/64

公开(公告)号：KR1019900011349A

公开(公告)日：1990-07-11

申请号：KR1019880017985

申请日：1988-12-30

Applicant: 한국전자통신연구원 ,  주식회사 케이티

Inventor： 강봉구 ,  박성호 ,  이영수 ,  배남진 ,  임대섭

IPC: H01L21/30

公开(公告)号：KR100396917B1

公开(公告)日：2003-09-02

申请号：KR1020000079748

申请日：2000-12-21

Applicant: 한국전자통신연구원

Inventor： 민병규 ,  김성일 ,  이경호 ,  박성호

IPC: H01L29/737

Abstract: PURPOSE: A fabrication method of an integrated circuit is provided to efficiently reduce a chip size by using a defined epitaxial layer of an HBT(Heterojunction Bipolar Transistor) as a resistor having a large resistance and using another defined epitaxial layer as a stabilizing resistor. CONSTITUTION: After removing an emitter cap layer(9), an emitter layer, and a surface of a base layer, base metal electrodes(11) is formed on both sides of an emitter metal electrode(10). After etching the base layer, a collector layer, and a surface of a second selective etch layer, the second selective etch layer is selectively etched compared to a subcollector layer. The entire subcollector layer is removed except for an active device part included region and a lowly resistive resistor(14) region. Collector metal electrodes(12) are formed on the active device part included region, the lowly resistive resistor(14), and defined regions of a second selective etch layer(3) having a high resistance. Then, the second selective etch layer(3) is selectively removed and a partial etching step is performed for isolation between the active and passive devices.

Abstract translation: 目的：提供集成电路的制造方法，以通过使用HBT（异质结双极晶体管）的限定的外延层作为具有大电阻的电阻器并使用另一定义的外延层作为稳定电阻器来有效地减小芯片尺寸。 构成：在去除发射极覆盖层（9），发射极层和基极层的表面之后，在发射极金属电极（10）的两侧形成基极金属电极（11）。 在蚀刻基极层，集电极层和第二选择性蚀刻层的表面之后，与子集电极层相比，选择性蚀刻第二选择性蚀刻层。 除了有源器件部分包括区域和低电阻电阻器（14）区域之外，整个子集电极层被去除。 集电极金属电极（12）形成在包括有源器件部分的区域，低电阻电阻器（14）以及具有高电阻的第二选择性蚀刻层（3）的限定区域上。 然后，选择性地去除第二选择性蚀刻层（3），并执行局部蚀刻步骤以在有源和无源器件之间进行隔离。

公开(公告)号：KR1020020050572A

公开(公告)日：2002-06-27

申请号：KR1020000079748

申请日：2000-12-21

Applicant: 한국전자통신연구원

Inventor： 민병규 ,  김성일 ,  이경호 ,  박성호

IPC: H01L29/737

Abstract: PURPOSE: A fabrication method of an integrated circuit is provided to efficiently reduce a chip size by using a defined epitaxial layer of an HBT(Heterojunction Bipolar Transistor) as a resistor having a large resistance and using another defined epitaxial layer as a stabilizing resistor. CONSTITUTION: After removing an emitter cap layer(9), an emitter layer, and a surface of a base layer, base metal electrodes(11) is formed on both sides of an emitter metal electrode(10). After etching the base layer, a collector layer, and a surface of a second selective etch layer, the second selective etch layer is selectively etched compared to a subcollector layer. The entire subcollector layer is removed except for an active device part included region and a lowly resistive resistor(14) region. Collector metal electrodes(12) are formed on the active device part included region, the lowly resistive resistor(14), and defined regions of a second selective etch layer(3) having a high resistance. Then, the second selective etch layer(3) is selectively removed and a partial etching step is performed for isolation between the active and passive devices.

Abstract translation: 目的：提供集成电路的制造方法，通过使用HBT（异质结双极晶体管）的限定外延层作为具有大电阻的电阻并使用另一限定的外延层作为稳定电阻来有效降低芯片尺寸。 构成：在发射极金属电极（10）的两侧形成有发射极覆盖层（9），发射极层和基极层的表面之后的基底金属电极（11）。 在蚀刻基底层，集电极层和第二选择性蚀刻层的表面之后，与子集电极层相比，选择性地蚀刻第二选择性蚀刻层。 除了有源器件部件包含区域和低电阻电阻器（14）区域之外，除去整个子集电极层。 集电极金属电极（12）形成在有源器件部分包含的区域，低电阻电阻（14）和具有高电阻的第二选择蚀刻层（3）的限定区域中。 然后，选择性地去除第二选择性蚀刻层（3），并且执行部分蚀刻步骤以在有源和无源器件之间进行隔离。

公开(公告)号：KR100296705B1

公开(公告)日：2001-08-07

申请号：KR1019970054790

申请日：1997-10-24

Applicant: 한국전자통신연구원

Inventor： 박성호 ,  박문평 ,  이태우

IPC: H01L29/737

Abstract: PURPOSE: A method for fabricating an integrated circuit using a hetero-junction bipolar transistor is provided to reduce a chip size by forming an resistant epitaxial layer in an epitaxial structure. CONSTITUTION: An epitaxial resistance layer(22) is formed on a semi-insulating compound semiconductor substrate(21). A sub-collector layer(23), a collector layer(24), a base layer(25), an emitter cap layer(27) are formed on the epitaxial resistance layer(22). An emitter metal layer(28) is deposited thereon. An emitter(26) connected with the emitter electrode(28) is formed by etching selectively the emitter cap layer(27) and the emitter layer(26). A base electrode(29) is formed on a selected portion of the exposed base layer(25). A base(25) is formed by etching the base layer(25) and the collector layer(24). A collector(24) is formed by etching the sub-collector layer(23). An electrode(30) is formed on a selected portion of the collector(24). A resistance electrode(31) is formed on a selected portion of the exposed epitaxial layer(22). A high resistance body(31) is formed by etching a part of the epitaxial resistance layer(22) and a part of the semi-insulating compound semiconductor substrate(21). A NiCr layer and a NoCr contact metal are deposited thereon. A low resistance body(34) is formed by etching selectively the NoCr contact metal.

公开(公告)号：KR1020010073652A

公开(公告)日：2001-08-01

申请号：KR1020000002427

申请日：2000-01-19

Applicant: 한국전자통신연구원

Inventor： 박문평 ,  이태우 ,  박성호 ,  민병규 ,  이경호

IPC: H01L29/737

Abstract: PURPOSE: An emitter structure heterojunction bipolar transistor and a method for manufacturing on a substrate using the same are provided to prevent an interconnection from becoming thinner or being cut when there is manufactured a diode for short circuiting a base-collector of a heterojunction bipolar transistor, a PN junction diode and a heterojunction bipolar transistor on the same substrate. CONSTITUTION: An emitter electrode(29), a base electrode(30) and a collector electrode(31) of a heterojunction bipolar transistor are consecutively formed by a lift-off process. An upper electrode(32) and a lower electrode(33) of a diode which short the second base layer(24b) and the second collector layer(23b) are formed at the same when the emitter(29) and the base electrode(30) of the heterojunction bipolar transistor are formed. An upper electrode(34) and a lower electrode(35) of a PN junction diode are formed at the same time when the base electrode(30) and the collector electrode(31) of the heterojunction bipolar transistor are formed. Since the upper electrode and the lower electrode of the PN junction diode and the upper electrode and the lower electrode of the diode which short the base-collector of the heterojunction bipolar transistor are formed at the same time when the emitter electrode, the base electrode and the collector electrode of the heterojunction bipolar transistor are formed, the emitter structure heterojunction bipolar transistor, the diode which shorts the base-collector of the heterojunction bipolar transistor and the PN junction diode can be easily manufactured on the same substrate.

Abstract translation: 目的：提供一种发射极结构异质结双极晶体管及其制造方法，用于在制造用于使异质结双极晶体管的基极集电极短路的二极管时互连变薄或切断， PN结二极管和同相衬底上的异质结双极晶体管。 构成：通过剥离处理连续地形成异质结双极晶体管的发射极（29），基极（30）和集电极（31）。 当发射极（29）和基极（30）之间形成有短路第二基极层（24b）和第二集电极层（23b）的二极管的上部电极（32）和下部电极（33） ）形成异质结双极晶体管。 在形成异质结双极晶体管的基极（30）和集电极（31）的同时，形成PN结二极管的上电极（34）和下电极（35）。 由于在发射电极，基极和基极集电体的同时形成PN结二极管的上电极和下电极以及上电极和短路异双极晶体管的基极集电极的二极管的下电极， 形成异质结双极晶体管的集电极，可以容易地在相同的衬底上制造发射极结构异质结双极晶体管，短路异质结双极晶体管和PN结二极管的基极集电极的二极管。

公开(公告)号：KR1020000038236A

公开(公告)日：2000-07-05

申请号：KR1019980053144

申请日：1998-12-04

Applicant: 주식회사 케이티 ,  한국전자통신연구원

Inventor： 박성호 ,  이태우 ,  박문평

IPC: H01L29/78

Abstract: PURPOSE: A fabrication method of HBT(heterojunction bipolar transistor) is provided to improve an emitter ohmic contact property and simplify the manufacturing process. CONSTITUTION: An HBT fabrication method comprises the following steps. An HBT epitaxial substrate sequentially formed a semiconductor(1), a buffer layer(2), a sub-collector(3), a collector(4), a base(5), an emitter(6), and emitter cap layers(7,8) is prepared by conventional processes. By using double mask layers(9,10) having different etching selectivity, surface protrusion patterns are formed on the HBT epitaxial substrate. The lower mask layer(9) made of a photoresist layer, and the upper mask layer(10) composed of a silicon nitride. Thereby, the surface protrusion pattern has s reverse T-shaped structure due to differency of etching selectivity. Using the surface protrusion pattern having reverse T-shaped structure, an emitter ohmic electrode is formed.

Abstract translation: 目的：提供HBT（异质结双极晶体管）的制造方法，以提高发射极欧姆接触性能并简化制造工艺。 构成：HBT制造方法包括以下步骤。 HBT外延基板依次形成半导体（1），缓冲层（2），子集电极（3），集电极（4），基极（5），发射极（6）和发射极盖层 7,8）通过常规方法制备。 通过使用具有不同蚀刻选择性的双掩模层（9,10），在HBT外延衬底上形成表面突出图案。 由光致抗蚀剂层制成的下掩模层（9）和由氮化硅构成的上掩模层（10）。 因此，由于蚀刻选择性的差异，表面突起图案具有相反的T形结构。 使用具有反T形结构的表面突起图案，形成发射极欧姆电极。

公开(公告)号：KR1020000027350A

公开(公告)日：2000-05-15

申请号：KR1019980045265

申请日：1998-10-28

Applicant: 한국전자통신연구원

Inventor： 박문평 ,  이태우 ,  박성호

IPC: H01L21/82

Abstract: PURPOSE: A method for manufacturing an integrated injection logic device having multi-collectors separated by an insulation layer is provided which has a high current gain, a planarized structure, a low base resistance of a heterojunction bipolar transistor and an increased breakdown voltage of a base-collector junction. CONSTITUTION: A method for manufacturing an integrated injection logic device comprises the steps of: sequentially forming a first conductive emitter cap layer(202), a first conductive emitter layer(203), a second conductive base layer(204), a first conductive collector layer(205) and a first conductive sub-collector layer(206) on a compound semiconductor layer; selectively etching the sub-collector layer, the collector layer and the base layer in the region other than an activation region of the first bipolar transistor; forming at least one groove by selectively etching the collector layer inside of the activation region to separate the collector layer inside of the activation region of the first bipolar transistor into at least two parts; filling an insulation layer(208) in the groove; forming an epitaxial layer(209) of a first conductivity on the exposed emitter layer; injecting a second conductive impurity ions into at least two portions of the epitaxial layer region to form a second bipolar transistor, the ions being injected into the depth of the emitter layer; injecting a first conductive impurity ions, using a mask covering the first and second bipolar transistors, to penetrate the emitter layer; and forming input electrode(212), output electrode(213) and injection electrode(212, 213, 214) in the second conductive impurity ion injection region and the sub-collector layer.

Abstract translation: 目的：提供一种用于制造具有由绝缘层分离的多个集电极的集成注入逻辑器件的方法，其具有高电流增益，平坦化结构，异质结双极晶体管的低基极电阻和基极的击穿电压的增加 收集器连接点。 构成：用于制造集成注入逻辑器件的方法包括以下步骤：顺序形成第一导电发射极帽层（202），第一导电发射极层（203），第二导电基底层（204），第一导电集电极 层（205）和化合物半导体层上的第一导电子集电极层（206）; 在除了第一双极晶体管的激活区域以外的区域中选择性地蚀刻副集电极层，集电极层和基极层; 通过选择性地蚀刻激活区域内的集电极层来形成至少一个沟槽，以将第一双极晶体管的激活区域内部的集电极层分离成至少两个部分; 在槽中填充绝缘层（208）; 在所述暴露的发射极层上形成第一导电性的外延层（209）; 将第二导电杂质离子注入所述外延层区域的至少两个部分以形成第二双极晶体管，所述离子被注入所述发射极层的深度; 使用覆盖第一和第二双极晶体管的掩模来注入第一导电杂质离子以穿透发射极层; 以及在第二导电杂质离子注入区域和副集电极层中形成输入电极（212），输出电极（213）和注入电极（212,213,214）。

公开(公告)号：KR100256695B1

公开(公告)日：2000-05-15

申请号：KR1019970037495

申请日：1997-08-06

Applicant: 한국전자통신연구원

Inventor： 박성호 ,  이태우 ,  박문평

IPC: H01L29/68

Abstract: PURPOSE: A method for fabricating a compound semiconductor device is to improve a coating characteristic by forming a via hole using a wet etching process, an ion implantation process and an ECR(electron cyclotron resonance) plasma dry etch process. CONSTITUTION: A pad electrode pattern(22) is formed on a compound semiconductor substrate(21). The compound semiconductor substrate is wet etched to a predetermined thickness using double etching mask patterns(23,24) which are formed beneath the compound semiconductor substrate. An ion implantation process to an exposed compound semiconductor substrate is carried out. A dry etch process is carried out to expose a portion of the pad electrode pattern. The double etching mask patterns are removed. A coating layer is formed according to a step difference of the compound semiconductor substrate. The pad electrode pattern is implemented with nickel, titanium, platinum and gold. The compound semiconductor substrate is formed to a thickness range of 50 micrometers to 100 micrometers.

Abstract translation: 目的：制造化合物半导体器件的方法是通过使用湿蚀刻工艺，离子注入工艺和ECR（电子回旋共振）等离子体干蚀刻工艺形成通孔来改善涂层特性。 构成：在化合物半导体衬底（21）上形成焊盘电极图案（22）。 使用形成在化合物半导体衬底下方的双蚀刻掩模图案（23,24）将化合物半导体衬底湿法蚀刻至预定厚度。 对暴露的化合物半导体衬底进行离子注入工艺。 执行干蚀刻工艺以暴露焊盘电极图案的一部分。 去除双蚀刻掩模图案。 根据化合物半导体基板的台阶差形成涂层。 焊盘电极图案用镍，钛，铂和金实现。 化合物半导体基板形成为50微米至100微米的厚度范围。

公开(公告)号：KR100243409B1

公开(公告)日：2000-02-01

申请号：KR1019960064707

申请日：1996-12-12

Applicant: 한국전자통신연구원 ,  주식회사 케이티

Inventor： 박문평 ,  이태우 ,  박성호

IPC: H01L21/20

Abstract: 본원 발명은 동일평면상에 PNP/NPN 화합물반도체 HBT의 에피층을 형성하는 방법에 관한 것으로, 감광막을 마스크로 하여 PNP 화합물반도체 HBT가 형성되는 영역 이외의 갈륨비소 기판(100)을 식각하여 돌출부를 형성하는 공정과, 상기 갈륨비소 기판 전면에 PNP 화합물반도체 HBT의 에피층을 성장시키는 공정과, 상기 PNP 화합물반도체 HBT의 에피층 전면에 NPN 화합물반도체 HBT의 에피층을 성장시키는 공정과, 상기 돌출부 상의 PNP 화합물반도체 HBT의 에피층 상에 성장된 NPN 화합물반도체 HBT의 에피층을 식각하는 공정을 포함하는 동일평면 상에 PNP/NPN 화합물반도체 HBT의 에피층을 성장시킴으로써, 에미터 상층구조 NPN/PNP 화합물반도체 HBT를 동일 평면상에 제작할 수 있으므로, NPN 화합물반도체 HBT 만으로 제작이 곤란했던 능동부하(active loads), 전류원(current sources)� � 푸시풀 증폭기(push-pull amplifier)를 제작하는 것이 가능한 효과를 가진다.