公开(公告)号：KR101382316B1

公开(公告)日：2014-04-08

申请号：KR1020120157483

申请日：2012-12-28

Applicant: 현대자동차주식회사

Inventor： 정영균 ,  홍경국 ,  이종석 ,  천대환

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/66068 ,  H01L29/1608 ,  H01L29/66666 ,  H01L29/7827

Abstract: The present invention relates to a method for manufacturing a semiconductor device, wherein the method comprises the steps of: sequentially forming an n-type epitaxial layer, a p-type epitaxial layer and n+ area on a first surface of a n+ type silicon carbide substrate; forming a photosensitive film pattern on the part of the n+ area; sequentially forming a first metal layer and a second metal layer on the photosensitive film pattern and n+ area; forming a first metal layer pattern and a second metal layer pattern exposing part of the n+ area by removing the photosensitive film pattern and the first and second metal layers positioned on the photosensitive film pattern; forming a preliminary trench by performing a first etching process for etching the part of the exposed n+ area by using the first metal layer pattern and the second metal layer pattern as a mask; and forming a trench by performing a second etching process for etching the preliminary trench, wherein the depth of the preliminary trench is equal or less than 1 micrometer.

Abstract translation: 本发明涉及一种制造半导体器件的方法，其中该方法包括以下步骤：在n +型碳化硅衬底的第一表面上依次形成n型外延层，p型外延层和n +区域 ; 在n +区域的一部分上形成感光膜图案; 在感光膜图案和n +区域上依次形成第一金属层和第二金属层; 通过去除感光膜图案和位于感光膜图案上的第一和第二金属层，形成暴露n +区域的一部分的第一金属层图案和第二金属层图案; 通过使用第一金属层图案和第二金属层图案作为掩模，通过执行用于蚀刻暴露的n +区域的一部分的第一蚀刻工艺来形成预备沟槽; 以及通过执行蚀刻所述预备沟槽的第二蚀刻工艺来形成沟槽，其中所述预备沟槽的深度等于或小于1微米。

公开(公告)号：KR101371495B1

公开(公告)日：2014-03-10

申请号：KR1020120157508

申请日：2012-12-28

Applicant: 현대자동차주식회사

Inventor： 이종석 ,  홍경국 ,  천대환 ,  정영균

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/66666 ,  H01L29/0688 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/42312 ,  H01L29/42316 ,  H01L29/4232 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/66734 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/7802 ,  H01L29/7813 ,  H01L29/7834 ,  H01L29/7827

Abstract: According to one embodiment of the present invention, a semiconductor element includes: an n+ type silicon carbide substrate; an n- type epi layer, a p type epi layer and an n+ region which are arranged in order on the first surface of the n+ type silicon carbide substrate; a trench which penetrates the n+ region and p type epi layer, is placed on the n- type epi layer, and includes a plurality of projections arranged on both lateral sides; a gate insulation film which is placed inside the trench; a gate electrode which is placed on the gate insulation film; an oxide film which is placed on the gate electrode; a source electrode which is placed on the p type epi layer, n+ region, and oxide film; and a drain electrode which is placed on the second surface of the n+ type silicon carbide substrate. The projections are stretched out to the p type epi layer.

Abstract translation: 根据本发明的一个实施例，半导体元件包括：n +型碳化硅衬底; 在n +型碳化硅衬底的第一表面上依次布置n型外延层，p型外延层和n +区域; 穿过n +区和p型epi层的沟槽被放置在n型外延层上，并且包括布置在两个侧面上的多个突起; 栅极绝缘膜，放置在沟槽内; 放置在栅极绝缘膜上的栅电极; 放置在栅电极上的氧化膜; 放置在p型外延层，n +区和氧化膜上的源电极; 以及放置在n +型碳化硅衬底的第二表面上的漏电极。 突起伸展到p型外延层。

公开(公告)号：KR101371491B1

公开(公告)日：2014-03-10

申请号：KR1020120157482

申请日：2012-12-28

Applicant: 현대자동차주식회사

Inventor： 정영균 ,  홍경국 ,  이종석 ,  천대환

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/66068 ,  H01L29/1608 ,  H01L29/66666 ,  H01L29/7827

Abstract: According to one embodiment of the present invention, a semiconductor element includes: an n+ type silicon carbide substrate; an n- type epi layer, a p type epi layer and an n+ region which are arranged in order on the first surface of the n+ type silicon carbide substrate; a trench which penetrates the n+ region and the p type epi layer and is placed on the n- type epi layer; a gate insulation film which is placed inside the trench on the n+ region and the p type epi layer; a gate electrode which is placed on the gate insulation film placed inside the trench; an oxide film which is placed on the gate electrode; a buffer layer which is placed on the gate insulation film placed on the n+ region and the p type epi layer; a source electrode which is placed on the buffer layer and the oxide film; and a drain electrode which is placed on the second surface of the n+ type silicon carbide substrate. The buffer is made of polycrystalline silicon.

Abstract translation: 根据本发明的一个实施例，半导体元件包括：n +型碳化硅衬底; 在n +型碳化硅衬底的第一表面上依次布置n型外延层，p型外延层和n +区域; 穿过n +区和p型epi层并且被放置在n型外延层上的沟槽; 栅极绝缘膜，其放置在n +区域和p型外延层上的沟槽内; 放置在沟槽内部的栅极绝缘膜上的栅电极; 放置在栅电极上的氧化膜; 放置在位于n +区域和p型epi层上的栅极绝缘膜上的缓冲层; 放置在缓冲层和氧化膜上的源电极; 以及放置在n +型碳化硅衬底的第二表面上的漏电极。 缓冲液由多晶硅制成。

公开(公告)号：KR101360070B1

公开(公告)日：2014-02-12

申请号：KR1020120155373

申请日：2012-12-27

Applicant: 현대자동차주식회사

Inventor： 이종석 ,  홍경국 ,  천대환 ,  정영균

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/0634 ,  H01L29/0878 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/66068 ,  H01L29/7813 ,  H01L29/1037 ,  H01L29/66666 ,  H01L29/7827

Abstract: A semiconductor element according to the embodiment of the present invention includes: an n+ type silicon carbide substrate; a plurality of n type pillar regions, a plurality of p type pillar regions, and an n- type epi layer which are placed on the first surface of the n+ type silicon carbide substrate; a p type epi layer and an n+ region which are placed in order on the n- type epi layer; a trench which penetrates the n+ region and the p type epi layer and is placed on the n- type epi layer; a gate insulation film which is placed in the trench; a gate electrode which is placed on the gate insulation film; an oxide film which is placed on the gate electrode; a source electrode which is placed on the p type epi layer, the n+ region, and the oxide film; and a drain electrode which is placed on the second surface of the n+ type silicon carbide substrate. The n type pillar regions and the p type pillar regions are placed inside the n- type epi layer, are apart from the trench, and are not placed on the area corresponding to the lower part of the trench.

Abstract translation: 根据本发明实施例的半导体元件包括：n +型碳化硅衬底; 设置在n +型碳化硅基板的第一表面上的多个n型支柱区域，多个p型支柱区域和n型外延层; p型外延层和n +区域，依次放置在n型外延层上; 穿过n +区和p型epi层并且被放置在n型外延层上的沟槽; 放置在沟槽中的栅极绝缘膜; 放置在栅极绝缘膜上的栅电极; 放置在栅电极上的氧化膜; 放置在p型外延层，n +区和氧化膜上的源电极; 以及放置在n +型碳化硅衬底的第二表面上的漏电极。 n型支柱区域和p型支柱区域放置在n型外延层内部，与沟槽分离，并且不放置在与沟槽的下部对应的区域上。

公开(公告)号：KR101338460B1

公开(公告)日：2013-12-10

申请号：KR1020120129747

申请日：2012-11-15

Applicant: 현대자동차주식회사

Inventor： 이종석 ,  홍경국 ,  천대환 ,  정영균

IPC: H01L21/336 ,  H01L29/78 ,  H01L21/265

CPC classification number: H01L29/66068 ,  H01L21/26586 ,  H01L29/1608

Abstract: A semiconductor device manufacturing method according to an embodiment of the present invention includes a step of forming an n type buffer layer on a first surface of an n+ type silicon carbide substrate, a step of forming an n- type epi layer on the n type buffer layer, a step of forming a p type epi layer on the n- type epi layer, a step of forming a first p+ region by injecting p+ ions on the p epi layer, a step of forming multiple first trenches by etching the first p+ region using a mask, a step of forming a first n+ region at the lower part and inside the side wall of the first trenches by injecting n+ ions into the first trenches using the mask, and a step of completing trenches by etching the lower part of the first trenches using the mask with the n+ ions injected vertically and diagonally. [Reference numerals] (AA,BB,CC) n^+ ion

Abstract translation: 根据本发明实施例的半导体器件制造方法包括在n +型碳化硅衬底的第一表面上形成n型缓冲层的步骤，在n型缓冲层上形成n型外延层的步骤 层，在n型外延层上形成p型外延层的步骤，通过在p外延层上注入p +离子形成第一p +区的步骤，通过用第一p +区蚀刻第一p +区形成多个第一沟槽的步骤 掩模，通过使用掩模将n +离子注入到第一沟槽中而在第一沟槽的下部和内侧形成第一n +区的步骤，以及通过蚀刻第一沟槽的下部来完成沟槽的步骤 使用正面和对角线注入n +离子的掩模的沟槽。 （标号）（AA，BB，CC）n ^ +离子

公开(公告)号：KR101339271B1

公开(公告)日：2013-12-09

申请号：KR1020120148600

申请日：2012-12-18

Applicant: 현대자동차주식회사

Inventor： 정영균 ,  홍경국 ,  이종석 ,  천대환

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/66068 ,  H01L21/049 ,  H01L21/76224 ,  H01L21/763 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7813

Abstract: A manufacturing method of a semiconductor device according to the present invention comprises; a step of forming an n-type epi-layer, a p-type epi-layer, and a first n+ area on a first surface of an n+type silicon carbide substrate in order; a step of forming a trench by passing through the first n+ area and the p-type epi-layer and etching a part of the n-type epi-layer; a step of forming a buffer layer on the trench and the first n+ area; a step of forming a buffer layer pattern on both side walls of the trench by etching the buffer layer; a step of forming a first silicon film on the first n+ area, the buffer layer pattern, and the trench; a step of forming a first silicon oxide film by oxidizing the first silicon film; a step of forming a first silicon oxide film pattern by removing the buffer layer pattern with an ashing process; a step of forming a second silicon film on the first silicon oxide film pattern and the trench; a step of forming a second silicon oxide film by oxidizing the second silicon film; and a step of forming a gate insulating film within the trench by etching the second silicon oxide film. The first silicon oxide film pattern is located on the top surface of the first n+ area and on the bottom surface of the trench.

Abstract translation: 根据本发明的半导体器件的制造方法包括： 在n +型碳化硅衬底的第一表面上依次形成n型外延层，p型外延层和第一n +区的步骤; 通过穿过第一n +区域和p型外延层形成沟槽并蚀刻n型外延层的一部分的步骤; 在沟槽和第一n +区域上形成缓冲层的步骤; 通过蚀刻缓冲层在沟槽的两个侧壁上形成缓冲层图案的步骤; 在第一n +区，缓冲层图案和沟槽上形成第一硅膜的步骤; 通过氧化第一硅膜形成第一氧化硅膜的步骤; 通过灰化处理去除缓冲层图案形成第一氧化硅膜图案的步骤; 在第一氧化硅膜图案和沟槽上形成第二硅膜的步骤; 通过氧化第二硅膜形成第二氧化硅膜的步骤; 以及通过蚀刻第二氧化硅膜在沟槽内形成栅极绝缘膜的步骤。 第一氧化硅膜图案位于第一n +区域的顶表面和沟槽的底表面上。

公开(公告)号：KR101339265B1

公开(公告)日：2013-12-09

申请号：KR1020120158603

申请日：2012-12-31

Applicant: 현대자동차주식회사

Inventor： 천대환 ,  이종석 ,  홍경국 ,  정영균

IPC: H01L21/337 ,  H01L29/808

CPC classification number: H01L29/0634 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/66068 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7802 ,  H01L29/7813

Abstract: A method for manufacturing a semiconductor device according to the prevent invention comprise; a step of sequentially forming a first insulating film and a first barrier layer on a first area of an n+type silicon carbide substrate; a step of forming a first barrier layer pattern by etching the first barrier layer; a step of forming a first insulating film pattern exposing a first portion of the first area of the n+type silicon carbide substrate by etching the first insulating film using the first barrier layer pattern as a mask; a step of forming a first type epi-layer on the first portion of the first area of the n+type silicon carbide substrate with epitaxial growth after removing the first barrier layer pattern; a step of sequentially forming a second insulating film and a second barrier layer on the first epi-layer and the first insulating film pattern; a step of forming a second barrier layer pattern by etching the second barrier layer; a step of forming a second insulating film pattern by etching the second insulating film using the second barrier layer pattern as a mask and of exposing a second portion of the first area of the n+type silicon carbide substrate by etching the first insulating film pattern using the second barrier layer pattern as a mask; and a step of forming a second epi-layer on the second portion of the first area of the n+type silicon carbide substrate with the epitaxial growth. The first portion of the first area of the n+type silicon carbide substrate is adjacent to the second portion of the first area of the n+type silicon carbide substrate.

Abstract translation: 根据本发明的制造半导体器件的方法包括： 在n +型碳化硅衬底的第一区上依次形成第一绝缘膜和第一阻挡层的步骤; 通过蚀刻第一阻挡层形成第一阻挡层图案的步骤; 通过使用第一阻挡层图案作为掩模蚀刻第一绝缘膜，形成暴露n +型碳化硅衬底的第一区域的第一部分的第一绝缘膜图案的步骤; 在除去第一阻挡层图案之后，在n +型碳化硅衬底的第一区域的第一部分上形成外延生长的步骤; 在第一外延层和第一绝缘膜图案上依次形成第二绝缘膜和第二阻挡层的步骤; 通过蚀刻第二阻挡层形成第二阻挡层图案的步骤; 通过使用第二阻挡层图案作为掩模蚀刻第二绝缘膜并且通过使用以下方式蚀刻第一绝缘膜图案来暴露n +型碳化硅衬底的第一区域的第二部分来形成第二绝缘膜图案的步骤 第二阻挡层图案作为掩模; 以及在外延生长的n +型碳化硅衬底的第一区域的第二部分上形成第二外延层的步骤。 n +型碳化硅衬底的第一区域的第一部分与n +型碳化硅衬底的第一区域的第二部分相邻。

公开(公告)号：KR1020130056454A

公开(公告)日：2013-05-30

申请号：KR1020110122075

申请日：2011-11-22

Applicant: 현대자동차주식회사

Inventor： 이종석 ,  홍경국

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/0657 ,  H01L29/0634 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/7825 ,  H01L29/7816

Abstract: PURPOSE: A LDMOS(Lateral Double diffusion Metal-Oxide-Semiconductor) device and a manufacturing method thereof are provided to reduce an on-resistance in a forward operation by increasing the doping density of an n-drift region. CONSTITUTION: An n-drift region(12) is formed on a p-type substrate(10). A p-body(14) is formed on one side of the upper side of the n-drift region. A p-epitaxial layer(16) is formed on the other side of the upper side of the n-drift region. A source electrode(28) is formed on an n+ source(18) and a p+ source(20). A gate oxide layer(26) is formed on the trench part of a field oxide layer(24). A drain electrode(30) is formed on an n+ drain(22).

Abstract translation: 目的：提供LDMOS（横向双扩散金属氧化物半导体）器件及其制造方法，以通过增加n漂移区域的掺杂密度来减小正向操作中的导通电阻。 构成：在p型衬底（10）上形成n漂移区（12）。 p体（14）形成在n漂移区域的上侧的一侧。 在n漂移区域的上侧的另一侧上形成p-外延层（16）。 源电极（28）形成在n +源极（18）和p +源极（20）上。 在场氧化物层（24）的沟槽部分上形成栅氧化层（26）。 漏电极（30）形成在n +漏极（22）上。

公开(公告)号：KR1020130049919A

公开(公告)日：2013-05-15

申请号：KR1020110114972

申请日：2011-11-07

Applicant: 현대자동차주식회사

Inventor： 홍경국 ,  이종석

IPC: H01L29/872

CPC classification number: H01L29/872 ,  H01L21/02529 ,  H01L21/26506 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/66143

Abstract: PURPOSE: A silicon carbide schottky barrier diode device and a manufacturing method thereof are provided to reduce an on-resistance by making a current flow in a conductive region with a high doping concentration. CONSTITUTION: A first n- epitaxial layer(11) is deposited on the upper side of an n+ substrate. An ohmic metal layer is bonded to the lower side of the n+ substrate. An n+ epitaxial layer(13) is formed by implanting n+ ions. The n+ epitaxial layer is arranged in the center of the first n- epitaxial layer. A schottky metal layer(14) is deposited on the n+ epitaxial layer. [Reference numerals] (14) Schottky metal; (15) Ohmic metal; (AA) n+ substrate; (BB) Forward current flow

Abstract translation: 目的：提供一种碳化硅肖特基势垒二极管器件及其制造方法，以通过在具有高掺杂浓度的导电区域中形成电流来降低导通电阻。 构成：第一n-外延层（11）沉积在n +衬底的上侧。 欧姆金属层结合到n +衬底的下侧。 通过注入n +离子形成n +外延层（13）。 n +外延层布置在第一n-外延层的中心。 肖特基金属层（14）沉积在n +外延层上。 （附图标记）（14）肖特基金属; （15）欧姆金属; （AA）n +底物; （BB）正向电流

公开(公告)号：KR1020130021771A

公开(公告)日：2013-03-06

申请号：KR1020110084234

申请日：2011-08-23

Applicant: 현대자동차주식회사

Inventor： 이용성 ,  홍경국 ,  이종석

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/66287 ,  H01L21/02293 ,  H01L21/20 ,  H01L29/7802

Abstract: PURPOSE: A semiconductor device is provided to reduce the on resistance of a device by preventing the diffusion of a depletion layer generated in a pn junction through a depletion diffusion preventing layer on the side of a trench gate. CONSTITUTION: An electric field dispersion layer(61) is formed on the lower side of a trench source(60). The electric field dispersion layer is formed by implanting P-type ions and disperses electric field concentrated on a lower oxidation layer(59). A depletion diffusion preventing layer(62) is formed on the upper side of an N- epitaxial layer(3). The depletion diffusion preventing layer prevents the diffusion of the depletion layer in a pn junction on the lower side of a trench source to affect a current flow. The depletion diffusion preventing layer forms an N+ region by an epitaxial growth method. [Reference numerals] (2) N+ substrate; (3) N- epitaxial layer

Abstract translation: 目的：提供一种半导体器件，以通过防止在pn结中产生的耗尽层扩散通过沟槽栅极侧的耗尽扩散防止层来降低器件的导通电阻。 构成：在沟槽源（60）的下侧形成电场分散层（61）。 通过注入P型离子并将电场分散在下部氧化层（59）上形成电场分散层。 耗尽扩散防止层（62）形成在N-外延层（3）的上侧。 耗尽扩散防止层防止在沟槽源的下侧的pn结中的耗尽层的扩散以影响电流。 耗尽扩散防止层通过外延生长法形成N +区域。 （附图标记）（2）N +基板; （3）N-外延层