公开(公告)号：US10985107B2

公开(公告)日：2021-04-20

申请号：US16583082

申请日：2019-09-25

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Jun Zhai

IPC: H01L23/48 ,  H01L21/44 ,  H01L23/538 ,  H01L23/488 ,  H01L23/00 ,  H01L25/18 ,  H01L21/66 ,  H01L23/522 ,  H01L23/528 ,  H01L23/58 ,  H01L23/498

Abstract: Stitched die structures, and methods for interconnecting die are described. In an embodiment, a stitched die structure includes a semiconductor substrate that includes a first die area of a first die and a second die area of a second die separate from the first die area. A back-end-of-the-line (BEOL) build-up structure spans over the first die area and the second die area, and includes a first metallic seal directly over a first peripheral area of the first die area, a second metallic seal directly over a second peripheral area of the second die area, and a die-to-die routing extending through the first metallic seal and the second metallic seal to electrically connect the first die to the second die.

公开(公告)号：US20190319626A1

公开(公告)日：2019-10-17

申请号：US16266604

申请日：2019-02-04

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Bahattin Kilic ,  Jie-Hua Zhao ,  Kunzhong Hu ,  Suk-Kyu Ryu

IPC: H03K19/177 ,  H05K1/02 ,  H01L23/31 ,  G06F15/78

Abstract: Multi-chip systems and structures for modular scaling are described. In some embodiments an interfacing bar is utilized to couple adjacent chips. For example, a communication bar may utilized to coupled logic chips, and memory bar may be utilized to couple multiple memory chips to a logic chip.

公开(公告)号：US10311938B2

公开(公告)日：2019-06-04

申请号：US15430747

申请日：2017-02-13

Applicant: Apple Inc.

Inventor： Sanjay Dabral

IPC: G11C11/4074 ,  G11C14/00 ,  H01L23/64 ,  H01L25/065 ,  H01L23/498 ,  H01L23/522 ,  G11C7/02 ,  G11C5/14 ,  G11C29/02 ,  H01L23/00 ,  H01L25/18

Abstract: One or more integrated circuits including at least one integrated circuit that is fabricated in a DRAM fabrication process. Capacitors in the DRAM-fabricated integrated circuit can be used for decoupling for logic components of the integrated circuits, and may be used for fine-grain on-chip PMUs. Embedded DRAM memories can be used instead of SRAM memories, with increased density and reduced leakage. More compact systems can be implemented using the integrated circuits.

公开(公告)号：US20170364141A1

公开(公告)日：2017-12-21

申请号：US15676322

申请日：2017-08-14

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  R. Stephen Polzin

IPC: G06F1/32 ,  G06F13/42

CPC classification number: G06F1/3296 ,  G06F1/3253 ,  G06F1/3287 ,  G06F13/4221 ,  G06F13/4282 ,  G06F2213/0024 ,  Y02D10/151 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D50/20

Abstract: An integrated circuit (IC) implements an industry standard-defined peripheral interconnect to connect to another integrated circuit or component in a system. The industry standard specification includes a software interface that is well-defined and implemented by various software in the system, and thus is desirable to retain. However, the physical interconnect in the systems employing the integrated circuit may be short, and thus the elaborate physical layer definition may consume more integrated circuit area and power than is otherwise desirable in the IC. The IC may implement a simpler and more power-efficient physical layer, reducing both power consumption and semiconductor substrate area consumption, in some embodiments.

公开(公告)号：US20160034025A1

公开(公告)日：2016-02-04

申请号：US14729335

申请日：2015-06-03

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  R. Stephen Polzin

IPC: G06F1/32 ,  G06F13/42

CPC classification number: G06F1/3296 ,  G06F1/3253 ,  G06F1/3287 ,  G06F13/4221 ,  G06F13/4282 ,  G06F2213/0024 ,  Y02D10/151 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D50/20

Abstract: An integrated circuit (IC) implements an industry standard-defined peripheral interconnect to connect to another integrated circuit or component in a system. The industry standard specification includes a software interface that is well-defined and implemented by various software in the system, and thus is desirable to retain. However, the physical interconnect in the systems employing the integrated circuit may be short, and thus the elaborate physical layer definition may consume more integrated circuit area and power than is otherwise desirable in the IC. The IC may implement a simpler and more power-efficient physical layer, reducing both power consumption and semiconductor substrate area consumption, in some embodiments.

Abstract translation: 集成电路（IC）实现工业标准定义的外围互连以连接到系统中的另一集成电路或组件。 行业标准规范包括由系统中的各种软件明确定义和实现的软件接口，因此是可取的。 然而，采用集成电路的系统中的物理互连可能很短，因此精细的物理层定义可能消耗比IC中其它方面所需要的更集成的电路面积和功率。 在一些实施例中，IC可以实现更简单和更节能的物理层，从而降低功耗和半导体衬底面积消耗。

公开(公告)号：US20150270258A1

公开(公告)日：2015-09-24

申请号：US14220293

申请日：2014-03-20

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Xiaofeng Fan ,  Geertjan Joordens

IPC: H01L27/02 ,  H02H9/04

CPC classification number: H01L27/0285 ,  H02H3/20 ,  H02H3/22 ,  H02H9/046

Abstract: ESD protection circuitry is disclosed. In one embodiment, an integrated circuit includes first and second sensor circuits. The first sensor circuit has a first resistive-capacitive (RC) time constant, while the second sensor circuit has a second RC time constant. The RC time constant of the first sensor circuit is at least one order of magnitude greater than that of the second sensor circuit. A first clamp transistor is coupled to and configured to be activated by the first sensor circuit responsive to the latter detecting an ESD event. A second clamp transistor is coupled to and configured to be activated by the second sensor circuit responsive to the latter detecting the ESD event.

Abstract translation: 公开了ESD保护电路。 在一个实施例中，集成电路包括第一和第二传感器电路。 第一传感器电路具有第一电阻 - 电容（RC）时间常数，而第二传感器电路具有第二RC时间常数。 第一传感器电路的RC时间常数比第二传感器电路的RC时间常数至少大一个数量级。 第一钳位晶体管耦合到并被配置为由第一传感器电路激活，响应于后者检测ESD事件。 第二钳位晶体管被耦合到并被配置为由第二传感器电路激活，响应于后者检测ESD事件。

公开(公告)号：US20250157991A1

公开(公告)日：2025-05-15

申请号：US19023053

申请日：2025-01-15

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Jun Zhai ,  Kwan-Yu Lai ,  Kunzhong Hu ,  Vidhya Ramachandran

IPC: H01L25/065 ,  H01L21/56 ,  H01L21/66 ,  H01L21/768 ,  H01L21/78 ,  H01L23/00 ,  H01L23/48 ,  H01L23/60 ,  H01L25/00

Abstract: Stitched die packaging techniques and structures are described in which reconstituted chips are formed using wafer reconstitution and die-stitching techniques. In an embodiment, a chip includes a reconstituted chip-level back end of the line (BEOL) build-up structure to connect a die set embedded in an inorganic gap fill material.

公开(公告)号：US12261132B2

公开(公告)日：2025-03-25

申请号：US18485709

申请日：2023-10-12

Applicant: Apple Inc.

Inventor： Vidhya Ramachandran ,  Sanjay Dabral ,  SivaChandra Jangam ,  Jun Zhai ,  Kunzhong Hu

IPC: H01L23/00 ,  H01L21/78 ,  H01L23/544 ,  H01L23/58

Abstract: Chip sealing structures and methods of manufacture are described. In an embodiment, a chip structure includes a main body area formed of a substrate, a back-end-of-the-line (BEOL) build-up structure spanning over the substrate, and chip edge sidewalls extending from a back surface of the substrate to a top surface of the BEOL build-up structure and laterally surrounding the substrate and the BEOL build-up structure. In accordance with embodiments, the chip structure may further include a conformal sealing layer covering at least a first chip edge sidewall of the chip edge sidewalls and a portion of the top surface of the BEOL build-up structure, and forming a lip around the top surface of the BEOL build-up structure.

公开(公告)号：US12119304B2

公开(公告)日：2024-10-15

申请号：US17321080

申请日：2021-05-14

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Zhitao Cao ,  Kunzhong Hu

IPC: H01L23/538 ,  H01L21/56 ,  H01L21/66 ,  H01L23/31 ,  H01L23/532 ,  H01L25/065

CPC classification number: H01L23/5384 ,  H01L21/56 ,  H01L22/12 ,  H01L23/31 ,  H01L23/53228 ,  H01L23/5386 ,  H01L25/0655

Abstract: Structures and methods of forming fine die-to-die interconnect routing are described. In an embodiment, a package includes a package-level RDL than spans across a die set and includes a plurality of die-to-die interconnects connecting contact pads between each die. In an embodiment, the plurality of die-to-die interconnects is embedded within one or more photoimageable organic dielectric layers.

公开(公告)号：US20240105702A1

公开(公告)日：2024-03-28

申请号：US18178820

申请日：2023-03-06

Applicant: Apple Inc.

Inventor： Chonghua Zhong ,  Jiongxin Lu ,  Kunzhong Hu ,  Jun Zhai ,  Sanjay Dabral

IPC: H01L25/18 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/36 ,  H01L25/00

CPC classification number: H01L25/18 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/36 ,  H01L24/08 ,  H01L24/13 ,  H01L24/32 ,  H01L24/80 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/13082 ,  H01L2224/32245 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: Semiconductor packages formed utilizing wafer reconstitution and optionally including an integrated heat spreader and methods of fabrication are described. In an embodiment, a semiconductor package includes a first package level, a second package level including one or more second-level chiplets, and a heat spreader bonded to the second package level with a metallic layer, which may include one or more intermetallic compounds formed by transient liquid phase bonding.