61.
    发明专利
    未知

    公开(公告)号:DE69032552D1

    公开(公告)日:1998-09-17

    申请号:DE69032552

    申请日:1990-10-18

    Abstract: The limiting circuit comprises a comparator (B), which makes the comparison between the output voltage (Vc) of the power device (T5, T6) and a predetermined reference voltage (Vrif). In the case wherein the output voltage (Vc) is just below the reference voltage (Vrif) the comparator (B) supplies a current to the load (L) suitable for preventing the output voltage from falling further below said reference voltage (Vrif).

    62.
    发明专利
    未知

    公开(公告)号:DE69633004T2

    公开(公告)日:2004-11-25

    申请号:DE69633004

    申请日:1996-05-31

    Inventor: PALARA SERGIO

    Abstract: A vertical structure, integrated bipolar transistor incorporating a current sensing resistor, comprises a collector region (1), a base region (3) overlying the collector region, and an emitter region over the base region. The emitter region comprises a buried region (5), a surface region (7), and a first vertical diffusion region (6) connecting the buried layer (5) to the surface region (7). A second vertical diffusion region (8) connects the buried emitter layer (5) periphery to a first surface contact (11), while the surface emitter region (7) is contacted, along three peripheral sides thereof, by a second surface contact (10). The transistor current flows from the substrate (1), through the base (3) to the buried emitter region (5). It is then conveyed into the vertical region (6), which represents a resistive path (R1), and on reaching the surface region (7) splits between two resistive paths (R2) included between the vertical region (6) and the surface contacts (10). These resistive paths form in combination the current sensing resistor incorporated to the transistor, whose terminals are led to the first (11) and second (10) surface contacts, respectively.

    63.
    发明专利
    未知

    公开(公告)号:DE69527702D1

    公开(公告)日:2002-09-12

    申请号:DE69527702

    申请日:1995-04-28

    Abstract: The invention concerns a method of detecting a spark produced by means of a spark coil (L) having a primary circuit (L') connected to a supply voltage generator (Vb) and a secondary circuit (L'') with the spark coil (L) being inserted in an electronic ignition device of an internal combustion motor. The method consists of the following phases: generation of a voltage signal (U) proportional to a voltage (VL) present on the primary circuit of the spark coil (L), comparison of the voltage signal (U) with a first, upper, threshold value (U1) by means of a comparator (C) with hysteresis, comparison by means of said comparator (C) of the voltage signal (U) with a second, lower, threshold value (U2) proportional to the supply voltage (Vb), detection of the duration of a voltage (Vc) output from the comparator (C), and signalling of the presence of the spark if said duration is greater than a reference value (B).

    64.
    发明专利
    未知

    公开(公告)号:DE69527201D1

    公开(公告)日:2002-08-01

    申请号:DE69527201

    申请日:1995-07-31

    Inventor: PALARA SERGIO

    Abstract: A voltage limiting circuit having a first and a second terminal between which is applied a voltage (Vs) to be limited of the type comprising at least one transistor (T2) having a first terminal connected to the first terminal of the circuit 1. This transistor T2 also comprises a second terminal kept at a reference voltage (E) and a control terminal coupled to the second terminal of the circuit 1 through at least one first equivalent resistive element (R'). The value of the equivalent resistive element (R') depends on the value of the voltage (Vs) to be limited so that the first transistor (T2) will have a temperature-stable breakdown voltage (Vcer).

    65.
    发明专利
    未知

    公开(公告)号:ITMI981376A1

    公开(公告)日:1999-12-16

    申请号:ITMI981376

    申请日:1998-06-16

    Abstract: The method comprises forming an implantation screening layer of predetermined thickness on the wafer, forming, in the screening layer, a first rectilinear, elongate opening having a first width, and at least a second rectilinear, elongate opening substantially parallel to the first opening and having a second width smaller than the first width is formed on the screening layer. The wafer is then subjected to ion implantation with two ion beams directed in directions substantially perpendicular to the longitudinal axes of the openings and inclined to the surface of the wafer at predetermined angles so as to strike the openings from two opposite sides. The thickness of the screening layer, the widths of the openings, and the angles of inclination of the ion beams being selected in a manner such that the beams strike the base of the first opening for substantially uniform doping of the underlying area of the wafer, but do not strike the base of the second opening. The novel method and apparatus enables selective doping by ion implantation to be performed without the use of a mask which is otherwise necessary for screening the second opening.

    69.
    发明专利
    未知

    公开(公告)号:IT1236797B

    公开(公告)日:1993-04-02

    申请号:IT2242889

    申请日:1989-11-17

    Abstract: The monolithic vertical-type semiconductor power device comprises an N+ type substrate (1) over which there is superimposed an N- type epitaxial layer (2) in which there is obtained aP type insulation pocket (3). Such pocket contains N type regions (4, 15) and P type regions (8) which in turn contain N+ type regions (11, 12; 13; 14) and of P type regions (6, 7, 9, 10) which define circuit components (T1, T2, T5) of the device. Insulation pocket (3) is wholly covered by a first metallisation (21, 30) connected to ground. Such metallisation (21, 30) is in turn protected by a layer of insulating material (18) suitable for allowing the crossing of metal tracks (20) or of a second metallisation (31) for the connection of the different components.

    70.
    发明专利
    未知

    公开(公告)号:IT1301729B1

    公开(公告)日:2000-07-07

    申请号:ITMI981376

    申请日:1998-06-16

    Abstract: The method comprises forming an implantation screening layer of predetermined thickness on the wafer, forming, in the screening layer, a first rectilinear, elongate opening having a first width, and at least a second rectilinear, elongate opening substantially parallel to the first opening and having a second width smaller than the first width is formed on the screening layer. The wafer is then subjected to ion implantation with two ion beams directed in directions substantially perpendicular to the longitudinal axes of the openings and inclined to the surface of the wafer at predetermined angles so as to strike the openings from two opposite sides. The thickness of the screening layer, the widths of the openings, and the angles of inclination of the ion beams being selected in a manner such that the beams strike the base of the first opening for substantially uniform doping of the underlying area of the wafer, but do not strike the base of the second opening. The novel method and apparatus enables selective doping by ion implantation to be performed without the use of a mask which is otherwise necessary for screening the second opening.

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