公开(公告)号：JPH0897168A

公开(公告)日：1996-04-12

申请号：JP16869395

申请日：1995-07-04

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： FERLA GIUSEPPE ,  FRISINA FERRUCCIO

IPC: H01L21/265 ,  H01L21/336 ,  H01L29/06 ,  H01L29/10 ,  H01L29/739 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a manufacturing method of highly integrated MOS power device. SOLUTION: Insulating gate layers 8 and insulating layers 11 are formed on a semiconductor layer 2, next to a plurality of slender windows having long edges 17 and short edges sectioning respectively exposed surface fine strips 16 are formed by selectively removing layers 8 and 11. Then the slender windows are implanted with a first dopant vertically thereto and perpendicularly to the layer 2 so as to be symmetrically tilted at the surface of the layer 2 making an angle. These angles depending upon the gross thickness of the layers 8 and 11 for preventing the first dopant from being implanted into the central fine strips of the fine strips 16 to form the pairs of source regions 6 extending along the edges 17 of respective windows, also separated by the central fine strips further symmetrically tilted making another angle to be implanted with a second dopant to form respective regions with two channel regions 5, extending to the under side of the long edges of respective windows finally implanted with a third dopant to form the regions aligned with the edges 17 of the windows using the layers 11 as masks.

公开(公告)号：JPH0846200A

公开(公告)日：1996-02-16

申请号：JP17871495

申请日：1995-07-14

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： FERLA GIUSEPPE ,  FRISINA FERRUCCIO

IPC: H01L29/74 ,  H01L21/265 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/739 ,  H01L29/749 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide an MOS technology power device having integrated circuit in which the series resistance of gate can be decreased without increasing the number of gate metal finger parts. SOLUTION: The MOS technology power device of integrated structure comprises a plurality of functional units of basic component formed in a lightly doped first conductivity type semiconductor layer 1 wherein the functional unit has a second conductivity type channel region 6 coated with a conductive insulation gate layer 8 including a polysilicon layer 5. The conductive insulation gate layer 8 has resistivity significantly lower than that of the polysilicon layer 5 superposed by a highly conductive layer 9. Since a resistance introduced by the polysilicon layer 5 is shunted by a resistance introduced by the highly conductive layer 9, total resistivity of the conductive insulation gate layer 8 is decreased.

公开(公告)号：JPH04215424A

公开(公告)日：1992-08-06

申请号：JP4555091

申请日：1991-02-20

Applicant: ST MICROELECTRONICS SRL

Inventor： SANTANGELO ANTONELLO ,  MAGRO CARMELO ,  FERLA GIUSEPPE ,  LANZA PAOLO

IPC: H01L21/265 ,  H01L21/28 ,  H01L21/285 ,  H01L21/329 ,  H01L21/768

Abstract: PURPOSE: To form the M-S contact of ohmic characteristic on a small doping region through dopant enrichment treatment on a contact surface by keeping the temperature and time of annealing treatment, which is to be performed after ion implantation on the surface of a semiconductor, at values without the possibility of changing functional characteristics in the structure of a device on the front surface of a wafer. CONSTITUTION: As a metal semiconductor ohmic contact forming treatment, the ion implantation of dopant is performed on the surface of a semiconductor 1. Next, a metal film 4 is deposited on the surface, where the ion implantation is performed, and then annealing treatment is performed considerably shorter than 60 minutes at a temperature considerably lower than 500 deg.C, so that dopant enrichment can be performed on the surface of the semiconductor 1 for forming the contact.

公开(公告)号：JP2618615B2

公开(公告)日：1997-06-11

申请号：JP15598395

申请日：1995-06-22

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： FERLA GIUSEPPE ,  FRISINA FERRUCCIO

IPC: H01L21/265 ,  H01L21/336 ,  H01L29/10 ,  H01L29/78

公开(公告)号：JPH0817849A

公开(公告)日：1996-01-19

申请号：JP15598395

申请日：1995-06-22

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： FERLA GIUSEPPE ,  FRISINA FERRUCCIO

IPC: H01L21/265 ,  H01L21/336 ,  H01L29/10 ,  H01L29/78

Abstract: PURPOSE: To reduce the manufacturing process of the channel region of a basic function unit and to reduce the ON resistance of a power device by forming the deep body part and the channel part of a body region only by ion implantation without performing any thermal diffusion treatment. CONSTITUTION: After a first dopant is selectively ion-implanted into a heavily doped part 5 in a direction that orthogonally crosses a semiconductor surface with a proper amount of dosage and an energy of ion implantation with an insulation gate layer 8 as a mask, a second dopant is selectively ion-implanted into a region 6 along a direction that is inclined at a prescribed angle in an orthogonally crossed direction, thus forming a body region 2. Then, a large dosage of third dopant is ion-implanted into the greatly doped part 5 to form a source region 7 that is nearly aligned to the edge part of the insulation gate layer 8, thus reducing the manufacturing process of the channel region of a basic function unit since no thermal diffusion treatment is made and reducing the on resistance of a power device.

公开(公告)号：JP2000357796A

公开(公告)日：2000-12-26

申请号：JP2000150927

申请日：2000-05-23

Applicant: ST MICROELECTRONICS SRL

Inventor： SCHILLACI ANTONIO ,  GRIMALDI ANTONIO ,  FERLA GIUSEPPE

IPC: H01L27/04 ,  H01L27/088 ,  H01L29/06 ,  H01L29/40 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To resist the high operating voltage whereto a device is subjected, by providing a voltage divider wherein an edge termination includes a plurality of MOS transistors connected in series with each other, and by providing connectively the edge termination between the terminals of a power constituting element whose drivings are impossible. SOLUTION: A device 1 comprises a MOSFET power transistor 21 connected with an edge termination 100. The power transistor 21 is connected in parallel with the series circuit comprising a diode 41 plus the series circuit comprising PMOS parasitic transistors 31, 32, 33, 34. To allow the current flowing from a source terminal S4 of the fourth PMOS parasitic transistor 34 to a source S of the MOSFET power transistor 21, these PMOS parasitic transistors 31-34 are switched on respectively when their respective sources overcome the respective threshold voltages of the PMOS parasitic transistors 31-34. Therefore, there is obtained a limit to the high operating voltage whereto the device 1 is subjected.

公开(公告)号：JP2000138232A

公开(公告)日：2000-05-16

申请号：JP28383899

申请日：1999-10-05

Applicant: ST MICROELECTRONICS SRL

Inventor： FRISINA FERRUCCIO ,  FERLA GIUSEPPE

IPC: G11C29/14 ,  G11C29/50 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a power device which does not raise problems related to threshold voltage, even if a normal insulating material is used for forming an insulating spacer and will not raise strain causing dislocations or cracks in silicon, even if another material such as silicon nitride is used. SOLUTION: This power semiconductor device has a second insulating material region 10 positioned at a side part of a polysilicon layer 5 and a first insulating material region 6, and at the upper side of a region 14 positioned near the opening at the upper side of an insulation layer body region 2 of a gate oxide layer 4, an oxide region 9 formed between a polysilicon region 5 and the second insulating material region 10, and an oxide spacer 8 formed in the upper side of a second material region.

公开(公告)号：JPH0864811A

公开(公告)日：1996-03-08

申请号：JP19326495

申请日：1995-07-28

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： FERLA GIUSEPPE ,  FRISINA FERRUCCIO

IPC: H01L29/78 ,  H01L29/739

Abstract: PROBLEM TO BE SOLVED: To prevent trigger-ons of a parasitic thyristor and to reduce static losses by allowing the sum of the common base current gain of a first bipolar junction type transistor and the current gain of a second bipolar junction type transistor to be 1 or greater. SOLUTION: A source region 11, a channel region 7, and an n-type layer 3 constitute a power MOSFET. The source region 11, a main body region 2, and the n-type layer 3 form the first npn bipolar junction type transistor T1. Furthermore, a substrate 5, the n-type layer 3, and the main body region constitute the second pnp bipolar junction type transistor T2. The sum of base current gains αn and αp of the npn bipolar junction type transistor T1 and pnp bipolar junction type transistor T2 are set so as to be 1 or greater. When the power MOSFET is driven on, both transistors are biased in the forward direction, resulting in αn +αp

公开(公告)号：JP2003133551A

公开(公告)日：2003-05-09

申请号：JP2002203102

申请日：2002-07-11

Applicant: ST MICROELECTRONICS SRL

Inventor： CEROFOLINI GIANFRANCO ,  FERLA GIUSEPPE

IPC: H01L21/8247 ,  H01L21/28 ,  H01L27/115 ,  H01L29/51 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L51/05 ,  H01L51/30 ,  H01L51/40 ,  H01L51/00

Abstract: PROBLEM TO BE SOLVED: To provide a hybrid structure in which organic molecules are bonded with conventional silicon-based microelectronic structure to function as carriers of charged particles. SOLUTION: This MOS transistor structure contains a dielectric oxide layer (3) formed between two silicon plates (1, 2), wherein the silicon plates (1, 2) extend outside the circumference of the oxide layer (3), forming an undercut (5) having a substantially rectangular cross section. The surfaces of the silicon plates (1, 2) are chemically changed to form functional groups (6, 7) that are different from those on the surfaces in the remaining part outside the undercut (5) portion. Organic molecules (8) each having a reversible reduction center and having a molecular length substantially the same as the width of the undercut (5), are selectively reacted with the functional groups (6, 7) on the undercut (5) to form a covalent bond at each end of the organic molecules.

公开(公告)号：JPH08213614A

公开(公告)日：1996-08-20

申请号：JP19759695

申请日：1995-08-02

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： FERLA GIUSEPPE ,  FRISINA FERRUCCIO

IPC: H01L21/60 ,  H01L21/768 ,  H01L23/12 ,  H01L23/482 ,  H01L23/495 ,  H01L23/522 ,  H01L29/417 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To reduce a parasitic resistance value and inductance of wire and pin by separating units comprising a plurality of function units with such a region of a semiconductor layer as no function unit is formed. SOLUTION: A semiconductor material layer 5 is selectively coated with an insulated gate layer 11 extending on a first doped region 7, and the gate layer 11 is made to contact gate metal meshes 101 and 102 connected to at least one gate metal pad, while surrounding a source metal plate 100. By connecting the gate metal pad to each pin P8 of a package with each bonding wire W8, all MOSFET units among all the MOSEFT units are connected in parallel. Thus, the maximum current capacity of the power device can be re- established, while each source electrode pin can be electrically speared according to individual purposes, resulting in significantly improved freedom in design.