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公开(公告)号：JPS60128743A
公开(公告)日：1985-07-09
申请号：JP23726583
申请日：1983-12-16
Applicant: FUJITSU LTD
Inventor： NAKAMURA OSAMU , MITA TERUYOSHI , KITANO YOSHIHIRO , NAKAHARA YASUHIRO , NEGISHI HITOSHI
IPC: H04B10/11
Abstract: PURPOSE:To reconstitute a highway without disconnecting nodes by using transmission lines bi-directionally and using a connected transmission line to consitute a communication bus if the transmission line of a current system or a stand-by system is connected to nodes adjacent to a disconnection position of the transmission line though the transmission line is disconnected. CONSTITUTION:In case of transmission of light to the transmission line, a prism 13 is pulled upward as shown in a figure (a), and an electric input signal is applied to a light emitting element 15, and this signal is converted to light and is transmitted to a transmission line 17. The light emitted to the side opposite to the transmission line can be monitored by a photodetector 16. In case of reception of light from the transmission line, the prism is pulled downward as shown in a figure (b). Then, the light from the transmission line 17 reaches the photodetector 16 through a route indicated by a solid line and is converted to an electric signal. This constitution is placed in positions 19, 20, 21, and 22 to use the optical transmission line in bi-directionally.
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公开(公告)号：JPS60128740A
公开(公告)日：1985-07-09
申请号：JP23726483
申请日：1983-12-16
Applicant: FUJITSU LTD
Inventor： KITANO YOSHIHIRO , MITA TERUYOSHI , NAKAHARA YASUHIRO , NEGISHI HITOSHI , NAKAMURA OSAMU
Abstract: PURPOSE:To shorten the retransmission time by adding a transmission packet order area into a packet format and providing a packet switching device with a packet order checking function and reproducing data transmission if data is dropped-out. CONSTITUTION:The packet transmission order area and a dropped-out packet number informing area are provided in data format packets flowed on a transmission line. Transmission data transmitted from a subsystem 23 is stored in a transmission packet buffer memory 20 of the packet switching device, and a subsystem control circuit 17 transmits a packet transmission request signal to a common control circuit 15. The common control circuit 15 detects an unused packet from frames passing data buffer registers 4, 5, 6, and 8 and adds the transmission packet order and transmits it onto the transmission line through a repeater 2. In the reception side, drop-out of coming packets is checked by a packet order checking circuit 18; and if drop-out is detected, retransmission request and the number of the packet whose retransmission is desired are reported to transmission/reception packet switching devices, and the transmission- packet switching device transmits desired data.
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公开(公告)号：JPS60128730A
公开(公告)日：1985-07-09
申请号：JP23726883
申请日：1983-12-16
Applicant: FUJITSU LTD
Inventor： NEGISHI HITOSHI , MITA TERUYOSHI , KITANO YOSHIHIRO , NAKAHARA YASUHIRO , NAKAMURA OSAMU
IPC: H04B10/07 , G01M11/00 , H04B3/46 , H04B10/00 , H04B10/032 , H04B10/035 , H04B10/077 , H04B10/079 , H04B10/275
Abstract: PURPOSE:To make investigations for setting again an optical cable unnecessary by transmitting a transmission line diagnostic command to a node whose abnormality is recognized in transmission line check of a data highway and detecting an erroneous set position of the transmission line and an erroneous connection order in accordance with the response. CONSTITUTION:A highway supervisory device (SV) transmits commands to operate line switchs (LSW)3, 6 and 7 of individual nodes and diagnoses the transmission line in a current system, a stand-by system, and a degnerated mode in order. If erroneous connection of the transmission line is detected as the result of diagnosis of the transmission line, the device SV releases loop back and instructs the pertinent node to by-pass both systems, and a test frame is transmitted from a system L0, and input sides of systems L0 and L1 are monitored to find the position of erroneous connection.
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公开(公告)号：JPS6010841A
公开(公告)日：1985-01-21
申请号：JP11730383
申请日：1983-06-29
Applicant: FUJITSU LTD
Inventor： KITANO YOSHIHIRO , MITA TERUYOSHI , NAKAHARA YASUHIRO , NAKAMURA OSAMU , NEGISHI HITOSHI
Abstract: PURPOSE:To attain detection even with duplicated node addresses by conducting address check of station nodes sequentially by an address check command from supervising node. CONSTITUTION:When a power source is applied on a data highway system, the supervising node SV starts a microprocessor so as to conduct an initial program load. When the operation is finished, the node address check command is transmitted from a command register. The node address is checked by using the response of the station node address from station nodes STO-STn. When the address check is finished, since the supervising node SV gives a neglecting release instruction to all the stations nodes STO-STn, all the station nodes STO-STn receive the next command.
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公开(公告)号：JPS5925449A
公开(公告)日：1984-02-09
申请号：JP13459082
申请日：1982-07-31
Applicant: Fujitsu Ltd
Inventor： TAKEYAMA AKIRA , TAZAKI TAKASHI , NOJIMA SATOSHI , MITA TERUYOSHI
CPC classification number: H04L7/00
Abstract: PURPOSE:To perform the effective switching for the clock signal source of a receiving station with a simple constitution, by executing a logical operation about the condition of a switch request signal and the condition under which the output of clock signal source is the same in phase to each other, and switching the results to prescribed values. CONSTITUTION:For a selecting/switching circuit in a deciding circuit, the left and right sides centering on a chain line show a common part CM and a part CH which can be increased for each channel. A frequency divider DV1 obtains a frequency FH of FO/(N-1) and a frequency FL of FO/(N+1) respectively, where FO and N show an input clock frequency of a receiving station and an integer respectively. A counter MOD delivers the least common multiple of (N-1).(N+ 1). A circuit LG performs an AND operation between a request signal CQR and the output E of a comparator CMP. Then an FF is reset by the next signal CRQ if an output Fout is equal to FH when the FF is set. Therefore, the output Fout is changed to FL.
Abstract translation: 目的：以简单的结构对接收站的时钟信号源进行有效切换，通过执行关于切换请求信号的条件的逻辑运算以及时钟信号源的输出在相位上相同的条件 并将结果切换到规定的值。 构成：对于决定电路中的选择/切换电路，以链线为中心的左右两侧显示公共部分CM和可以为每个通道增加的部分CH。 分频器DV1分别获得FO /（N-1）的频率FH和FO /（N + 1）的频率FL，其中FO和N分别表示接收站的输入时钟频率和整数。 计数器MOD提供（N-1）（N + 1）的最小公倍数。 电路LG在请求信号CQR和比较器CMP的输出E之间执行“与”运算。 然后，当FF置位时，如果输出Fout等于FH，则FF由下一个信号CRQ复位。 因此，输出Fout变为FL。
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Patent Agency Ranking
公开(公告)号：JPS58170251A
公开(公告)日：1983-10-06
申请号：JP5297182
申请日：1982-03-31
Applicant: FUJITSU LTD
Inventor： NAKAMURA OSAMU , MITA TERUYOSHI
Abstract: PURPOSE:To detect simply an ineffective packet, by reading a transmitted address added to the packet and collating it with the state of each station. CONSTITUTION:Stations 2-7 are connected to a transmission line of loop form. An address is given to each station. A monitor SV1 detects and deletes ineffective packets which exist on the transmission line and are not assigned. The monitor is provided with an address table which records whether or not each station receives a packet. The monitoring device reads the address to be transmitted for the packet transmitted on the transmission line and compares it with the data in the address table. The packet having no correspondence possible for reception is made ineffective. Since the monitoring device monitors the address to be transmitted in the packet only, the monitoring device makes normal operation independently of the content of the packet.
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公开(公告)号：JPS57204662A
公开(公告)日：1982-12-15
申请号：JP8918281
申请日：1981-06-10
Applicant: FUJITSU LTD
Inventor： MITA TERUYOSHI , YATSUHOSHI AKIMASA , HIGUCHI TAIHOU
IPC: H04B14/04 , H04L27/10 , H04L27/156
Abstract: PURPOSE:To obtain an economical data communication processing system, by demodulating original signals directly from pulse-code-modulated FSK signals without converting them into analog signals once. CONSTITUTION:Signals obtained by pulse-code-modulating FSK waves are set to a register 2 at a time interval which is equal to the sampling cycle, and then, successively transferred to another register 3. Outputs of both the registers 2 and 3 are connected to a decoder 4, and, when the code bit of the registers 3 and 2 is 1 (negative) and 0 (positive), respectively, namely at the zero-crossing point from the negative to the positive, a counter reset signal CR is generated. At any combination of code bits other than the above, a counter step-advancing signal CPU is generated. The counter reset signal CR and the counter step-advancing signal CPU thus generated control a counter 5. The counter output corresponding to the signal cycle is compared with a prescribed value at a comparator 7 and the compared result is sent to a flip flop 8 and outputted as received data RD.
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公开(公告)号：JPS57137945A
公开(公告)日：1982-08-25
申请号：JP2379781
申请日：1981-02-20
Applicant: FUJITSU LTD
Inventor： HOSHI FUMIO , MITA TERUYOSHI , SATOU MASAO
IPC: G06F9/38
Abstract: PURPOSE:To get rid of a dead machine cycle, and to process an instruction efficiently, by selecting an output of an address generating circuit, and controlling a general purpose register. CONSTITUTION:The second address generating circuit 20 receives an output of an instruction decoding circuit 8, generates an address and inputs it to a comparing circuit 24 and an address selecting circuit 22. An output address of the first address generating circuit 10 is also inputted to the comparing circuit 24 and the address selecting circuit 22. The output address of the address generating circuit 10 is inputted to the address selecting circuit 22 through the third address generating circuit 21. This input signal is delayed by a constant interval of time from the output of the first address generating circuit 10. To the address selecting circuit 22, the outputs of each address generating circuit 10, 20 and 21 are inputted. The address selecting circuit 22 selects outputs of 3 kinds and drives a general purpose register 9.
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公开(公告)号：JPS57137944A
公开(公告)日：1982-08-25
申请号：JP2379681
申请日：1981-02-20
Applicant: FUJITSU LTD
Inventor： HOSHI FUMIO , MITA TERUYOSHI , SATOU MASAO
IPC: G06F9/38
Abstract: PURPOSE:To get rid of a dead loss in executing the operation, and to elevate the processing capacity, by additionally providing an instruction decoding circuit on a storage device, and reading and operating in advance the contents of a general register by an output of this circuit prior to execution of the instruction. CONSTITUTION:To an instruction decoding circuit 10, an output of a storage device 1 is inputted, its output is divided into 2 branches, and one branch is inputted to a general address generating circuit 5 and the other branch is inputted to an operation controlling circuit 6. In the instruction decoding circuit 10, as soon as execution of an instruction is started, A of a general register 4 is read out in the first cycle, and the operation controlling circuit 6 drives the general address generating circuit 5 by an instruction decoding circuit 3 in the second cycle. Since read-out of A of the general register 4 has been completed already, read-out of B of the general register 4 and write of its B are executed continuously, and the operation of A+B is executed by the continuous timing in the machine cycle of 3 cycles.
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公开(公告)号：JPS57109439A
公开(公告)日：1982-07-07
申请号：JP18680680
申请日：1980-12-26
Applicant: FUJITSU LTD
Inventor： KITANO YOSHIHIRO , MITA TERUYOSHI
IPC: H04B10/556 , H04B10/00 , H04B10/032 , H04B10/035 , H04B10/079 , H04B10/275 , H04B10/29 , H04L12/42 , H04L12/437
Abstract: PURPOSE:To reconstitute a loop, by providing a means, which detects the lowering of the level of an optical signal, in the station node and monitoring this means by a highway monotor device. CONSTITUTION:When the optical level from optical transmission lines L0 and L1 is lowered, a transmission abnormality detecting part 6 detects this lowering and reports it to a control part 3. The control part 3 stores this information in a node status register and writes contents of the node status register into the node response part in a frame DF flowed to transmission lines L0 and L1 and reports it to a highway monitor device. Meanwhile, the highway monitor device analyzes the node response and discriminates the lowering of the level of the optical signal to issue a node command, and transmission lines are reconstituted by switching of transmission lines from the current system to the stand-by system, issuing of a folding command to a specific station node, etc.
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