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    Translation of input/output addresses to memory addresses
    61.
    发明专利
    Translation of input/output addresses to memory addresses 未知

    公开(公告)号：AU2010355813A1

    公开(公告)日：2012-12-20

    申请号：AU2010355813

    申请日：2010-11-08

    Applicant: IBM

    Inventor： CRADDOCK DAVID ,  GREGG THOMAS ,  GREINER DAN ,  LAIS ERIC NORMAN

    IPC: G06F13/16 ,  G06F12/10

    Abstract: An address provided in a request issued by an adapter is converted to an address directly usable in accessing system memory. The address includes a plurality of bits, in which the plurality of bits includes a first portion of bits and a second portion of bits. The second portion of bits is used to index into one or more levels of address translation tables to perform the conversion, while the first portion of bits are ignored for the conversion. The first portion of bits are used to validate the address.

    TRANSLATION OF INPUT/OUTPUT ADDRESSES TO MEMORY ADDRESSES
    63.
    发明专利
    TRANSLATION OF INPUT/OUTPUT ADDRESSES TO MEMORY ADDRESSES 未知

    公开(公告)号：CA2800636A1

    公开(公告)日：2011-12-29

    申请号：CA2800636

    申请日：2010-11-08

    Applicant: IBM

    Inventor： CRADDOCK DAVID ,  GREGG THOMAS ,  GREINER DAN ,  LAIS ERIC NORMAN

    IPC: G06F13/16 ,  G06F12/10

    Abstract: An address provided in a request issued by an adapter is converted to an address directly usable in accessing system memory. The address includes a plurality of bits, in which the plurality of bits includes a first portion of bits and a second portion of bits. The second portion of bits is used to index into one or more levels of address translation tables to perform the conversion, while the first portion of bits are ignored for the conversion. The first portion of bits are used to validate the address.

    METODO, SISTEMA Y PRODUCTO DE PROGRAMA DE COMPUTADORA PARA CONTROL DE CONGESTION ADAPTABLE EN CARRILES VIRTUALES PARA ARQUITECTURA DE ETHERNET DE CENTRO DE DATOS.
    64.
    发明专利
    METODO, SISTEMA Y PRODUCTO DE PROGRAMA DE COMPUTADORA PARA CONTROL DE CONGESTION ADAPTABLE EN CARRILES VIRTUALES PARA ARQUITECTURA DE ETHERNET DE CENTRO DE DATOS. 未知

    公开(公告)号：MX2010003014A

    公开(公告)日：2010-03-31

    申请号：MX2010003014

    申请日：2008-09-04

    Applicant: IBM

    Inventor： DECUSATIS CASIMER ,  GREGG THOMAS

    IPC: H04L12/56 ,  H04L47/27

    Abstract: Se describe un método para el control de congestión en donde la congestión es controlada de manera adaptable en una red de Ethernet de Centro de Datos (DCE). Se reciben paquetes en por lo menos un carril virtual en la red de DCE. Se calcula una velocidad de llegada de paquetes absoluta o relativa en un periodo de tiempo. La velocidad de llegada de paquetes absoluta o relativa es comparada con por lo menos un primer umbral y un segundo umbral. Si la velocidad de llegada de paquetes absoluta o relativa se incrementa más allá del primer umbral, se provoca que la velocidad de transmisión de paquete disminuya. Si la velocidad de llegada de paquetes absoluta o relativa es menor que un segundo umbral, se provoca que la velocidad de transmisión de paquetes se incremente.

    65.
    发明专利
    未知

    公开(公告)号：DE10016937B4

    公开(公告)日：2004-04-29

    申请号：DE10016937

    申请日：2000-04-05

    Applicant: IBM

    Inventor： GOLDRIAN GOTTFRIED ,  GREGG THOMAS

    IPC: G04G7/00 ,  G06F1/14 ,  G06F1/04 ,  H03L7/00 ,  H03K21/40

    Abstract: The basic idea comprised of the present invention is to decentralize the generation of time information without suffering from the cost disadvantages expectable due to use of prior art techniques necessary for synchronizing and correcting a plurality instead of only one or two of time suppliers caused by said decentralization. This is achieved by the approach not to readjust the oscillator(s), but, instead, to accept the inaccuracy of the physical device 'oscillator' but to measure its inaccuracy and to correct it with the aid of a continuos correction calculation which is advantageously done in a digital way under usage of ETS input information and system oscillator output information.

    DETECTING LOST AND OUT OF ORDER POSTED WRITE PACKETS IN A PERIPHERAL COMPONENT INTERCONNECT (PCI) EXPRESS NETWORK
    69.
    发明专利
    DETECTING LOST AND OUT OF ORDER POSTED WRITE PACKETS IN A PERIPHERAL COMPONENT INTERCONNECT (PCI) EXPRESS NETWORK 未知

    公开(公告)号：CA2743111C

    公开(公告)日：2017-11-07

    申请号：CA2743111

    申请日：2010-05-28

    Applicant: IBM

    Inventor： GREGG THOMAS

    IPC: G06F13/38 ,  G06F13/42

    Abstract: An apparatus, method and computer program for processing packets in a peripheral component interconnect express (PCIe) network provide means for receiving a PCIe posted write packet at a receiving device, the PCIe posted write packet including a received tag identifier and a requesting device identifier identifying a requesting device. An expected tag identifier is determined for the requesting device. The received tag identifier is compared to the expected tag identifier. An error flag is set if the received tag identifier does not match the expected tag identifier.

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