公开(公告)号：JPH10105308A

公开(公告)日：1998-04-24

申请号：JP23564297

申请日：1997-09-01

Applicant: IBM

Inventor： GOLDRIAN GOTTFRIED ,  TAST HANS-WERNER

IPC: G06F3/00 ,  G06F13/42 ,  H04L12/40

Abstract: PROBLEM TO BE SOLVED: To transmit a time critical command to a transmission partner while watching a time limit and to use an optimum bus line relating to a transmission band width by switching a bus between an initial state and a second state. SOLUTION: In the initial state of the bus, a data transmission direction is scheduled from a unit A to the unit B for a half bus 211, that is one segment of the bus line, and data are transmitted from the unit B to the unit A in the half bus 212, that is the other segment of the bus line. As a transmitted function, by making a transmission direction invertible in the half bus 211 (212), the bus is converted from the initial state to the entire band width. That is, in the case that the large amount of the data are transmitted from the unit A to the unit B, even though the transmission direction of the half bus 211 is not changed (213), the transmission direction of the half bus 212 is changed (214). Thereafter, the data transmission direction of the half bus 214 is inverted again.

公开(公告)号：JP2001147903A

公开(公告)日：2001-05-29

申请号：JP2000278528

申请日：2000-09-13

Applicant: IBM

Inventor： MICHAEL IGNATOSKI ,  HELLER THOMAS J JR ,  GOLDRIAN GOTTFRIED

IPC: G06F12/06 ,  G06F12/08 ,  G06F15/16

Abstract: PROBLEM TO BE SOLVED: To provide a novel structure for a highly scalable high-performance shared memory computer system having simple production possibility. SOLUTION: The intra-node bus mechanism of a peculiar type connects respective system cells in each of nodes to the other respective cells inside the same node. An inter-node bus can be shared by plural nodes. Even when all the memory subsets inside all the cells of the shared memory system can be accessed by all processors, bus competition to occur inside a shared memory is remarkably reduced. A node directory automatically manages the coherence of all data to be changed inside all processor caches in the computer system and provides data coherence over all the nodes in the computer system.

公开(公告)号：JPH10171712A

公开(公告)日：1998-06-26

申请号：JP18157397

申请日：1997-07-07

Applicant: IBM

Inventor： GOLDRIAN GOTTFRIED

IPC: G06F13/36 ,  G06F12/08 ,  G06F13/42 ,  G06F15/167

Abstract: PROBLEM TO BE SOLVED: To make it possible to connect external data traffic to a multi- processor computer system without exerting influence upon the usability of a pin belonging to a 2nd level cache chip by using a processor bus for the transmission of I/O data (or external data of an optional sort) to the 2nd level cache chip. SOLUTION: Each processor 200 is connected to respective 2nd level cache chips 201 through respective processor buses. Each 2nd level cache chip 201 includes a memory bank 203, a directory for tracing the position of a different cache line and a processor bus switch 202 for connecting a correct memory bank to a processor bus. Each chip 201 is connected to a memory card 205 through a memory bus 204. A memory card includes a storage control device 206, a memory address driver and a memory data multiplexing means.

公开(公告)号：DE3272860D1

公开(公告)日：1986-10-02

申请号：DE3272860

申请日：1982-05-24

Applicant: IBM DEUTSCHLAND ,  IBM

Inventor： GOLDRIAN GOTTFRIED

IPC: G01R13/28 ,  G01R31/3177 ,  G06F11/25 ,  G01R31/28 ,  G06F11/22

Abstract: A logic signal analyzer comprises a time measuring adapter. Only some of the input channels of the signal analyzer are used to store input data when an event occurs, i. e. when one or more of the binary input signals change their value. A time counter (7) is provided for measuring the time that has elapsed between two consecutive events. The contents of the time counter are transferred to the logic analyzer on the remaining input channels. … In another mode of operation only the signal on a predetermined input channel is used to control the storing operation. The time counter is reset after each storing operation. … In still another mode of operation the signal on a predetermined channel can be used to inhibit or allow the storing of the signals on the remaining input channels.

公开(公告)号：DE3271524D1

公开(公告)日：1986-07-10

申请号：DE3271524

申请日：1982-03-25

Applicant: IBM DEUTSCHLAND ,  IBM

Inventor： GOLDRIAN GOTTFRIED ,  RUDOLPH VOLKER DR

IPC: B41J2/425 ,  G01D15/08 ,  H03K17/0422 ,  H04N1/23 ,  B41J3/20

Abstract: To obtain a good print quality in metal paper printers, the print current, after ignition of the arc, must be rapidly reduced to a fraction of the value necessary for ignition. For this purpose, two transistor power stages (T3, T4) are connected to the print electrode (2). Their partial currents form the print current, whose rapid reduction after ignition of the arc is obtained by the two transistor power stages being operated at voltages (U2, U3) of different magnitude. The second transistor stage (T4) is operated at a voltage (U3), whose magnitude corresponds to the drop in potential occurring upon ignition between the grounded metal layer (3) of the record carrier (4) and the print electrode. As a result, the second transistor stage is switched off when a diode (D) connected to it becomes non-conductive.

公开(公告)号：DE10016937B4

公开(公告)日：2004-04-29

申请号：DE10016937

申请日：2000-04-05

Applicant: IBM

Inventor： GOLDRIAN GOTTFRIED ,  GREGG THOMAS

IPC: G04G7/00 ,  G06F1/14 ,  G06F1/04 ,  H03L7/00 ,  H03K21/40

Abstract: The basic idea comprised of the present invention is to decentralize the generation of time information without suffering from the cost disadvantages expectable due to use of prior art techniques necessary for synchronizing and correcting a plurality instead of only one or two of time suppliers caused by said decentralization. This is achieved by the approach not to readjust the oscillator(s), but, instead, to accept the inaccuracy of the physical device 'oscillator' but to measure its inaccuracy and to correct it with the aid of a continuos correction calculation which is advantageously done in a digital way under usage of ETS input information and system oscillator output information.

公开(公告)号：DE10016937A1

公开(公告)日：2001-01-18

申请号：DE10016937

申请日：2000-04-05

Applicant: IBM

Inventor： GOLDRIAN GOTTFRIED ,  GREGG THOMAS

IPC: G04G7/00 ,  G06F1/14 ,  G06F1/04 ,  H03L7/00 ,  H03K21/40

Abstract: System clocking frequencies in computer systems, particularly networked computer systems, are corrected so as to match an external reference source by the application of a continual digital computer procedure, via an ETS- (absolute external time source) information input and system oscillator output information with part of the used time signal being regularly changed for correction of an imprecise time signal having an ETS reference time source. This takes place in a circuit which includes a controller which regularly reads or measures the external reference time and the system time.

公开(公告)号：DE19636381C1

公开(公告)日：1998-03-12

申请号：DE19636381

申请日：1996-09-09

Applicant: IBM

Inventor： GOLDRIAN GOTTFRIED ,  TAST HANS-WERNER

IPC: G06F3/00 ,  G06F13/42 ,  G06F13/38

Abstract: The processor bus has two transmission lines which can be switched between a first operating mode in which the lines are arranged in two groups for transmission in opposite directions and a second operating mode in which both groups have the same transmission direction. The switching between the alternate operating modes is effected by switching the transmission direction of one of the bus line groups.

公开(公告)号：CA1221571A

公开(公告)日：1987-05-12

申请号：CA452132

申请日：1984-04-16

Applicant: IBM

Inventor： GOLDRIAN GOTTFRIED ,  RUDOLPH VOLKER ,  RUPPERT WERNER ,  WOHNSDORF MANFRED

IPC: G03F5/00

Abstract: METHOD OF REPRODUCING IMAGES WITH GREY VALUES The invention concerns a method of reproducing images with grey values,using picture elements (PELS) for the different grey values, which are represented by dot patterns with a different distribution and arrangement of the individual dots, characterized in that for each grey value there is a stock of quasi-equivalent grey value pels, and that for representing each grey value of an original to be reproduced, a pel corresponding to this grey value is selected from the associated stock of quasi-equivalent grey value patterns.

公开(公告)号：DE10018190C2

公开(公告)日：2003-04-17

申请号：DE10018190

申请日：2000-04-12

Applicant: IBM

Inventor： GOLDRIAN GOTTFRIED

IPC: G06F1/08 ,  H03K5/26 ,  H03L7/00 ,  G06F1/12 ,  H03K19/007 ,  G06F1/04

Abstract: A system and method for observing the two clocking phase signals, finding a point in time when said signals have a phase coincidence which is good enough for fulfilling a phase difference requirement (e.g. 20 ps), and switching from one clock source to the other. The essential idea is not to compare the phases directly but to generate an auxiliary signal out of the two clock signals which is easier to handle in order to find that desired point in time and which reflects all desired properties of the time dependent phase shift between said clock signals. At a predetermined location in the cycle of both clock signals (e.g. its positive transition) a pulse is generated out of each of the clock signals with matched identical delay elements located very close to each other on the same chip for both signals. As they match they produce exactly the same pulse widths. The absolute length of the pulse width is of minor relevance as long as the length of the pulses is the same within close limits. Both signals are ANDed. Thus, in the resulting signal a pulse emerge at every positive transition of the oscillator clocks when the phase alignment of the clock signals is closer than the width of the transition pulse. When the alignment is bad-no signal will be produced.