DYNAMIC ADDRESS TRANSLATION WITH FRAME MANAGEMENT

    公开(公告)号:CA2701086A1

    公开(公告)日:2009-07-16

    申请号:CA2701086

    申请日:2009-01-05

    Applicant: IBM

    Abstract: What is disclosed is a set key and clear frame management function defined for a machine architecture of a computer system. In one embodiment, a machine instruction is obtained which identifies a first and second general register. Obtained from the first general register is a frame size field indicating whether a storage frame is one of a small block or a large block of data. Obtained from the second general register is an operand address of a storage frame upon which the instruction is to be performed. If the storage frame is a small block, the instruction is performed only on the small block. If the indicated storage frame is a large block of data, an operand address of an initial first block of data within the large block of data is obtained from the second general register. The frame management instruction is performed on all blocks starting from the initial first block.

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