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公开(公告)号:EP2862089A4
公开(公告)日:2015-09-02
申请号:EP12879101
申请日:2012-11-26
Applicant: IBM
Inventor: GREINER DAN , ROGERS ROBERT , SITTMANN GUSTAV
CPC classification number: G06F12/1027 , G06F9/3004 , G06F9/3824 , G06F12/1009 , G06F2212/683
Abstract: A first and a second operand are compared. If they are equal, the contents of register R1+1 are stored at the second-operand location, and the specified CPU or CPUs in the configuration are cleared of all TLB table entries of the designated type formed through the use of the replaced entry in storage, and all lower-level TLB table entries formed through the use of the cleared higher-level TLB table entries. A valid DAT table entry is replaced with a new entry, and the Translation Lookaside Buffer (TLB) is purged of any copies of (at least) the single entry on all CPUs in the configuration. If the first and second operands are unequal, the second operand is loaded at the first-operand location. The comparison result is indicated by the condition code. A method, system and a computer program product are provided.
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公开(公告)号:WO2013186266A3
公开(公告)日:2014-02-13
申请号:PCT/EP2013062165
申请日:2013-06-12
Inventor: JACOBI CHRISTIAN , SLEGEL TIMOTHY , SHUM CHUNG-LUNG KEVIN , SITTMANN GUSTAV
CPC classification number: G06F9/30076 , G06F9/30 , G06F9/30047 , G06F9/30145 , G06F9/34 , G06F9/383 , G06F12/0815 , G06F12/0862 , G06F12/123 , G06F12/126 , G06F2212/6028
Abstract: Executing a Next Instruction Access Intent instruction by a computer. The processor obtains an access intent instruction indicating an access intent. The access intent is associated with an operand of a next sequential instruction. The access intent indicates usage of the operand by one or more instructions subsequent to the next sequential instruction. The computer executes the access intent instruction. The computer obtains the next sequential instruction. The computer executes the next sequential instruction, which comprises based on the access intent, adjusting one or more cache behaviors for the operand of the next sequential instruction.
Abstract translation: 由计算机执行下一条指令访问意图指令。 处理器获得指示访问意图的访问意图指令。 访问意图与下一个顺序指令的操作数相关联。 访问意图表示在下一个顺序指令之后的一个或多个指令的操作数的使用。 计算机执行访问意图指令。 计算机获取下一个顺序指令。 计算机执行下一个顺序指令,其包括基于访问意图,调整下一个顺序指令的操作数的一个或多个缓存行为。
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公开(公告)号:WO2013186606A8
公开(公告)日:2014-12-18
申请号:PCT/IB2012056736
申请日:2012-11-26
Inventor: GREINER DAN , ROGERS ROBERT , SITTMANN GUSTAV
IPC: G06F12/10
CPC classification number: G06F12/1027 , G06F9/3004 , G06F9/3824 , G06F12/1009 , G06F2212/683
Abstract: A first and a second operand are compared. If they are equal, the contents of register R1 + 1 are stored at the second-operand location, and the specified CPU or CPUs in the configuration are cleared of all TLB table entries of the designated type formed through the use of the replaced entry in storage, and all lower-level TLB table entries formed through the use of the cleared higher-level TLB table entries. A valid DAT table entry is replaced with a new entry, and the Translation Lookaside Buffer (TLB) is purged of any copies of (at least) the single entry on all CPUs in the configuration. If the first and second operands are unequal, the second operand is loaded at the first-operand location. The comparison result is indicated by the condition code. A method, system and a computer program product are provided.
Abstract translation: 比较第一和第二操作数。 如果它们相等,则寄存器R1 + 1的内容存储在第二操作数位置,并且配置中指定的CPU或CPU将清除通过使用替换的条目形成的指定类型的所有TLB表项 存储和通过使用清除的更高级TLB表条目形成的所有较低级别的TLB表条目。 有效的DAT表条目被替换为新条目,并且翻译后备缓冲区(TLB)被清除组态中所有CPU上的(至少)单个条目的任何副本。 如果第一和第二操作数不相等,则第二个操作数被加载到第一个操作数位置。 比较结果由条件码表示。 提供了一种方法,系统和计算机程序产品。
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公开(公告)号:AU2012382781B2
公开(公告)日:2016-06-02
申请号:AU2012382781
申请日:2012-11-26
Applicant: IBM
Inventor: GREINER DAN , ROGERS ROBERT , SITTMANN GUSTAV
IPC: G06F12/10
Abstract: A first and a second operand are compared. If they are equal, the contents of register R
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公开(公告)号:HRP20170402T1
公开(公告)日:2017-05-19
申请号:HRP20170402
申请日:2017-03-10
Applicant: IBM
Inventor: MACCHIANO ANGELO , TARCZA RICHARD , WINTER ALEXANDRA , SITTMANN GUSTAV , STEVENS JERRY
IPC: G06F9/54
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公开(公告)号:DE112013002155T5
公开(公告)日:2015-01-15
申请号:DE112013002155
申请日:2013-06-12
Applicant: IBM
Inventor: JACOBI CHRISTIAN , SLEGEL TIMOTHY , SHUM CHUNG-LUNG KEVIN , SITTMANN GUSTAV
Abstract: Ausführen eines Befehls zur Art des Zugriffs auf den nächsten Befehl durch einen Computer. Der Prozessor bezieht einen Zugriffsartbefehl, der eine Zugriffsart angibt. Die Zugriffsart ist einem Operanden eines nächsten sequenziellen Befehls zugehörig. Die Zugriffsart gibt eine Verwendung des Operanden durch einen oder mehrere Befehle im Anschluss an den nächsten sequenziellen Befehl an. Der Computer führt den Zugriffsartbefehl aus. Der Computer bezieht den nächsten sequenziellen Befehl. Der Computer führt den nächsten sequenziellen Befehl aus, was ein Anpassen einer oder mehrerer Cache-Verhaltensweisen für den Operanden des nächsten sequenziellen Befehls auf Grundlage der Zugriffsart aufweist.
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公开(公告)号:DE602006012843D1
公开(公告)日:2010-04-22
申请号:DE602006012843
申请日:2006-07-13
Applicant: IBM
Inventor: ADLUNG INGO , CHOI JONG HYUK , FRANKE HUBERTUS , HELLER LISA , HOLDER WILLIAM , MANSELL RAY , OSISEK DAMIAN , PHILLEY RANDALL , SCHWIDEFSKY MARTIN , SITTMANN GUSTAV
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公开(公告)号:SI2862089T1
公开(公告)日:2019-03-29
申请号:SI201231515
申请日:2012-11-26
Applicant: IBM
Inventor: GREINER DAN , ROGERS ROBERT , SITTMANN GUSTAV
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公开(公告)号:HRP20150385T1
公开(公告)日:2015-06-19
申请号:HRP20150385
申请日:2015-04-02
Applicant: IBM
Inventor: SITTMANN GUSTAV , CRADDOCK DAVID , GREGG THOMAS , FARRELL MARK , EASTON JANET , LAIS ERIC NORMAN
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公开(公告)号:PT2229631E
公开(公告)日:2012-05-11
申请号:PT09700560
申请日:2009-01-05
Applicant: IBM
Inventor: HELLER LISA , OSISEK DAMIAN , SITTMANN GUSTAV , GAINEY CHARLES JR , GREINER DAN , SLEGEL TIMOTHY
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