公开(公告)号：US12182062B1

公开(公告)日：2024-12-31

申请号：US17961833

申请日：2022-10-07

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Altug Koker ,  Aravindh Anantaraman ,  Elmoustapha Ould-Ahmed-Vall ,  Valentin Andrei ,  Nicolas Galoppo Von Borries ,  Varghese George ,  Mike Macpherson ,  Subramaniam Maiyuran ,  Joydeep Ray ,  Lakshminarayanan Striramassarma ,  Scott Janus ,  Brent Insko ,  Vasanth Ranganathan ,  Kamal Sinha ,  Arthur Hunter ,  Prasoonkumar Surti ,  David Puffer ,  James Valerio ,  Ankur N. Shah

IPC: G06F15/78 ,  G06F7/544 ,  G06F7/575 ,  G06F7/58 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/80 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06N3/08 ,  G06T15/06

Abstract: Methods and apparatus relating to techniques for multi-tile memory management. In an example, a graphics processor includes an interposer, a first chiplet coupled with the interposer, the first chiplet including a graphics processing resource and an interconnect network coupled with the graphics processing resource, cache circuitry coupled with the graphics processing resource via the interconnect network, and a second chiplet coupled with the first chiplet via the interposer, the second chiplet including a memory-side cache and a memory controller coupled with the memory-side cache. The memory controller is configured to enable access to a high-bandwidth memory (HBM) device, the memory-side cache is configured to cache data associated with a memory access performed via the memory controller, and the cache circuitry is logically positioned between the graphics processing resource and a chiplet interface.

公开(公告)号：US20240232094A1

公开(公告)日：2024-07-11

申请号：US18405933

申请日：2024-01-05

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  David Puffer ,  Prasoonkumar Surti ,  Lakshminarayanan Striramassarma ,  Vasanth Ranganathan ,  Kiran C. Veernapu ,  Balaji Vembu ,  Pattabhiraman K

IPC: G06F12/0877 ,  G06F12/0802 ,  G06F12/0806 ,  G06F12/0846 ,  G06F12/0855 ,  G06F12/0868 ,  G06F12/0893 ,  G06F12/126 ,  G06T1/60

CPC classification number: G06F12/0877 ,  G06F12/0802 ,  G06F12/0806 ,  G06F12/0848 ,  G06F12/0855 ,  G06F12/0868 ,  G06F12/126 ,  G06T1/60 ,  G06F12/0893

Abstract: One embodiment provides circuitry coupled with cache memory and a memory interface, the circuitry to compress compute data at multiple cache line granularity, and a processing resource coupled with the memory interface and the cache memory. The processing resource is configured to perform a general-purpose compute operation on compute data associated with multiple cache lines of the cache memory. The circuitry is configured to compress the compute data before a write of the compute data via the memory interface to the memory bus, in association with a read of the compute data associated with the multiple cache lines via the memory interface, decompress the compute data, and provide the decompressed compute data to the processing resource.

公开(公告)号：US20240004713A1

公开(公告)日：2024-01-04

申请号：US18363339

申请日：2023-08-01

Applicant: Intel Corporation

Inventor： Abhishek R. APPU ,  Altug KOKER ,  Balaji VEMBU ,  Joydeep RAY ,  Kamal SINHA ,  Prasoonkumar SURTI ,  Kiran C. VEERNAPU ,  Subramaniam MAIYURAN ,  Sanjeev S. Jahagirdar ,  Eric J. Asperheim ,  Guei-Yuan Lueh ,  David Puffer ,  Wenyin Fu ,  Nikos Kaburlasos ,  Bhushan M. Borole ,  Josh B. Mastronarde ,  Linda L. Hurd ,  Travis T. Schluessler ,  Tomasz Janczak ,  Abhishek Venkatesh ,  Kai Xiao ,  Slawomir Grajewski

IPC: G06F9/50 ,  G06F1/329 ,  G06F9/48 ,  G06T1/20 ,  G06T1/60 ,  G06T15/00

CPC classification number: G06F9/5016 ,  G06F9/5044 ,  G06F1/329 ,  G06F9/4893 ,  G06T1/20 ,  G06T1/60 ,  G06T15/005 ,  Y02D10/00 ,  G06T2200/28

Abstract: In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.

公开(公告)号：US11816040B2

公开(公告)日：2023-11-14

申请号：US17712109

申请日：2022-04-02

Applicant: Intel Corporation

Inventor： Vidhya Krishnan ,  Siddhartha Chhabra ,  David Puffer ,  Ankur Shah ,  Daniel Nemiroff ,  Utkarsh Y. Kakaiya

IPC: G06F12/00 ,  G06F12/14 ,  G06F11/10 ,  G06F12/02

CPC classification number: G06F12/1433 ,  G06F11/1004 ,  G06F12/0292 ,  G06F12/1408 ,  G06F12/1466 ,  G06F12/1483

Abstract: Device memory protection for supporting trust domains is described. An example of a computer-readable storage medium includes instructions for allocating device memory for one or more trust domains (TDs) in a system including one or more processors and a graphics processing unit (GPU); allocating a trusted key ID for a TD of the one or more TDs; creating LMTT (Local Memory Translation Table) mapping for address translation tables, the address translation tables being stored in a device memory of the GPU; transitioning the TD to a secure state; and receiving and processing a memory access request associated with the TD, processing the memory access request including accessing a secure version of the address translation tables.

公开(公告)号：US20230306552A1

公开(公告)日：2023-09-28

申请号：US17827305

申请日：2022-05-27

Applicant: Intel Corporation

Inventor： David Cowperthwaite ,  David Puffer ,  Ankur Shah ,  Alan Previn Teres Alexis ,  Satyeshwar Singh

IPC: G06T1/20 ,  G06T15/00 ,  G06F9/455

CPC classification number: G06T1/20 ,  G06F9/455 ,  G06T15/005

Abstract: Described herein is a partitional graphics processor including a display controller including hardware display virtualization. One embodiment provides a graphics processor comprising a system interface including a first virtual interface and a second virtual interface, a render engine to perform graphics rendering operations, and a display engine including hardware display virtualization. The render engine is configured to perform a first rendering operation in response to a command received via the first virtual interface and a second rendering operation in response to a command received via the second virtual interface. The display engine configured to present output of the first rendering operation via a first physical display plane that is associated with the first virtual interface and present output of the second rendering operation via a second physical display plane that is associated with the second virtual interface.

公开(公告)号：US20230306551A1

公开(公告)日：2023-09-28

申请号：US17702301

申请日：2022-03-23

Applicant: Intel Corporation

Inventor： Vidhya Krishnan ,  Niranjan Cooray ,  David Puffer ,  Ronald Silvas ,  Durgaprasad Bilagi ,  Aditya Navale

IPC: G06T1/20 ,  G06F12/02 ,  G06T1/60 ,  G06T9/00

CPC classification number: G06T1/20 ,  G06F12/0223 ,  G06T1/60 ,  G06T9/00 ,  G06F2212/401

Abstract: Described herein is a graphics processor comprising a processing resource configured to perform processing operations, a codec configured to compress and decompress data associated with the processing operations, and circuitry configured to calculate a metadata address for a compressed surface based on a flat virtual memory address mapping between the address of the compressed surface and the metadata address. The compressed surface is to store data associated with a processing operation to be performed by the processing resource and the metadata address is a virtual address that stores compression metadata for the compressed surface. The circuitry can configure the codec to access the compressed surface based on the compression metadata.

公开(公告)号：US20230298125A1

公开(公告)日：2023-09-21

申请号：US17827444

申请日：2022-05-27

Applicant: Intel Corporation

Inventor： Hema Chand Nalluri ,  Jeffery S. Boles ,  David Cowperthwaite ,  Aditya Navale ,  Prasoonkumar Surti ,  Arthur Hunter ,  Vasanth Ranganathan ,  Joydeep Ray ,  David Puffer ,  Ankur Shah ,  Vidhya Krishnan ,  Kritika Bala ,  Aravindh Anantaraman ,  Michael Apodaca ,  Kenneth Daxer

IPC: G06T1/20 ,  G06T15/00 ,  G06T1/60 ,  G06F9/48 ,  G06F9/50

CPC classification number: G06T1/20 ,  G06T15/005 ,  G06T1/60 ,  G06F9/4881 ,  G06F9/5061 ,  G06F9/505 ,  G06T2200/16

Abstract: Described herein is a partitionable graphics processor having multiple render front ends. The partitions of the graphics processor maintain render functionality when partitioned and enable fault isolation and independent multi-client rendering.

公开(公告)号：US20230297526A1

公开(公告)日：2023-09-21

申请号：US17832305

申请日：2022-06-03

Applicant: Intel Corporation

Inventor： David Puffer ,  Ankur Shah ,  Niranjan Cooray ,  Bryan White ,  Balaji Vembu ,  Hema Chand Nalluri ,  Kritika Bala

IPC: G06F13/24 ,  G06F13/16

CPC classification number: G06F13/24 ,  G06F13/1668 ,  G06T1/20

Abstract: Embodiments described herein provide techniques to facilitate scalable interrupts and workload submission for a virtualized graphics processor. The techniques include memory-based interrupt reporting and shared work queue submission for multiple software domains.

公开(公告)号：US20230297440A1

公开(公告)日：2023-09-21

申请号：US17827373

申请日：2022-05-27

Applicant: Intel Corporation

Inventor： David Cowperthwaite ,  Kenneth Daxer ,  Jeffery S. Boles ,  Hema Chand Nalluri ,  Aditya Navale ,  Prasoonkumar Surti ,  Arthur Hunter ,  Vasanth Ranganathan ,  Joydeep Ray ,  David Puffer ,  Aravindh Anantaraman ,  Ankur Shah ,  Vidhya Krishnan ,  Kritika Bala

IPC: G06F9/50 ,  G06T1/20

CPC classification number: G06F9/5077 ,  G06F9/5016 ,  G06T1/20

Abstract: Described herein is a partitionable graphics processor having a plurality of flexibly partitioned processing resources. One embodiment provides a graphics processor comprising a plurality of processing resources configurable to be flexibly partitioned into a plurality of resource partitions and circuitry to compose multiple graphics processor device partitions from the plurality of resource partitions. The multiple graphics processor device partitions are configurable to be asymmetrically composed of different types of functional units.

公开(公告)号：US20230297421A1

公开(公告)日：2023-09-21

申请号：US17827346

申请日：2022-05-27

Applicant: Intel Corporation

Inventor： David Cowperthwaite ,  Kenneth Daxer ,  Aditya Navale ,  Prasoonkumar Surti ,  Arthur Hunter ,  Hema Chand Nalluri ,  Jeffery S. Boles ,  Vasanth Ranganathan ,  Joydeep Ray ,  David Puffer ,  Aravindh Anantaraman ,  Ankur Shah ,  Vidhya Krishnan ,  Kritika Bala ,  Michael Apodaca

IPC: G06F9/48 ,  G06T1/60 ,  G06T1/20 ,  G06F9/50

CPC classification number: G06F9/4881 ,  G06T1/60 ,  G06T1/20 ,  G06F9/5038 ,  G06F9/5055

Abstract: Described herein is a partitional graphics processor having multiple hard partitions with separate software execution and fault domains. One embodiment provides a graphics processor comprising a system interface and a plurality of graphics processing resources coupled with the system interface. The plurality of graphics processing resources is configurable to be partitioned into a plurality of isolated device partitions, each isolated device partition configured for fault isolation and independent concurrent execution of workloads associated with a plurality of clients, and the system interface is configured to present each of the plurality of isolated device partitions as a virtual function.