中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

108 records (took 0.036 seconds)

    Multi-use package architecture
    62.
    发明授权
    Multi-use package architecture 有权

    公开(公告)号：US11929295B2

    公开(公告)日：2024-03-12

    申请号：US17677843

    申请日：2022-02-22

    Applicant: Intel Corporation

    Inventor： Eng Huat Goh ,  Jiun Hann Sir ,  Min Suet Lim ,  Richard C. Stamey ,  Chu Aun Lim ,  Jimin Yao

    IPC: H01L23/31 ,  H01L23/00 ,  H01L23/528 ,  H01L23/538

    CPC classification number: H01L23/3121 ,  H01L23/5283 ,  H01L23/5389 ,  H01L24/10 ,  H01L24/82 ,  H01L2924/01029 ,  H01L2924/1811

    Abstract: A semiconductor package is disclosed, which comprises a substrate, one or more dies on a first side of the substrate, and a plurality of interconnect structures having a first pitch and coupled to a second side of the substrate. The interconnect structures may attach the substrate to a board. The substrate may include a first interconnect layer having a second pitch. The first interconnect layer may be coupled to the one or more dies through second one or more interconnect layers. Third one or more interconnect layers between the first interconnect layer and the interconnect structures may translate the first pitch to the second pitch. The substrate may include a recess on a section of the second side of the substrate. The semiconductor package may further include one or more components within the recess and attached to the second side of the substrate.

    Chassis interconnect for an electronic device
    65.
    发明授权
    Chassis interconnect for an electronic device 有权

    公开(公告)号：US11445608B2

    公开(公告)日：2022-09-13

    申请号：US16903845

    申请日：2020-06-17

    Applicant: Intel Corporation

    Inventor： Chee How Lim ,  Eng Huat Goh ,  Jon Sern Lim ,  Khai Ern See ,  Min Suet Lim ,  Tin Poay Chuah ,  Yew San Lim

    IPC: H05K1/14 ,  H01R12/61 ,  H05K1/11

    Abstract: An electronic device may include a chassis. The electronic device may include a first electronic component that may include a first substrate and a first interconnect. The electronic device may include a second electronic component that may include a second substrate and a second interconnect. The second substrate may be physically separated from the first substrate. An electrical trace may be coupled to the chassis of the electronic device. The electrical trace may be sized and shaped to interface with the first interconnect of the first electronic component. The electrical trace may be sized and shaped to interface with the second interconnect of the second electronic component. The first electronic component and the second electronic component may be in electrical communication through the electrical trace coupled to the chassis of the electronic device.

    Board to board interconnect
    66.
    发明授权
    Board to board interconnect 有权

    公开(公告)号：US11304299B2

    公开(公告)日：2022-04-12

    申请号：US17008222

    申请日：2020-08-31

    Applicant: Intel Corporation

    Inventor： Chee Ling Wong ,  Wil Choon Song ,  Khang Choong Yong ,  Eng Huat Goh ,  Mohd Muhaiyiddin Bin Abdullah ,  Tin Poay Chuah

    IPC: H05K1/11 ,  H05K1/14 ,  H05K1/02

    Abstract: A system for board-to-board interconnect is described herein. The system includes a first printed circuit board (PCB) having a first recess along a first edge of the first PCB that exposes a first solder pad on a layer of the first PCB. The system also includes a second PCB having a second recess along a second edge of the second PCB that exposes a second solder pad on a layer of the second PCB. The second recess is complementary to the first recess to allow the first PCB to mate with the second PCB. The first solder pad is aligned with the second solder pad when the first PCB is mated with the second PCB. The system additionally includes an assembly configured to electronically couple the first solder pad with the second solder pad.

    CHASSIS INTERCONNECT FOR AN ELECTRONIC DEVICE
    69.
    发明申请
    CHASSIS INTERCONNECT FOR AN ELECTRONIC DEVICE 有权

    公开(公告)号：US20210100101A1

    公开(公告)日：2021-04-01

    申请号：US16903845

    申请日：2020-06-17

    Applicant: Intel Corporation

    Inventor： Chee How Lim ,  Eng Huat Goh ,  Jon Sern Lim ,  Khai Ern See ,  Min Suet Lim ,  Tin Poay Chuah ,  Yew San Lim

    IPC: H05K1/14 ,  H05K1/11 ,  H01R12/61

    Abstract: An electronic device may include a chassis. The electronic device may include a first electronic component that may include a first substrate and a first interconnect. The electronic device may include a second electronic component that may include a second substrate and a second interconnect. The second substrate may be physically separated from the first substrate. An electrical trace may be coupled to the chassis of the electronic device. The electrical trace may be sized and shaped to interface with the first interconnect of the first electronic component. The electrical trace may be sized and shaped to interface with the second interconnect of the second electronic component. The first electronic component and the second electronic component may be in electrical communication through the electrical trace coupled to the chassis of the electronic device.

Patent Agency Ranking