HYBRID PARALLEL/SERIAL BUS INTERFACE

    公开(公告)号:CA2467851A1

    公开(公告)日:2003-06-05

    申请号:CA2467851

    申请日:2002-11-19

    Abstract: A hybrid serial/parallel bus interface has a data block demultiplexing devic e (40). The data block demultiplexing device (40) has an input configured to receive a data block and demultiplexes the data block into a plurality of nibbles (42(2)). For each nibble, a parallel to serial converter (42i) converts the nibble into serial data. A line transfers each nibble's serial data. A serial to parallel converter (46i) converts each nibble's serial dat a to recover that nibble. A data block reconstruction device (48) combines the recovered nibbles into the data block.

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