公开(公告)号：WO0232018A3

公开(公告)日：2002-08-29

申请号：PCT/US0131612

申请日：2001-10-10

Applicant: INTERDIGITAL TECH CORP

Inventor： OLESEN ROBERT L ,  AXNESS TIMOTHY A ,  KAZAKEVICH LEONID

IPC: H04L5/16 ,  H03G3/20 ,  H03M1/18 ,  H04B1/16 ,  H04B1/707 ,  H04B7/005 ,  H04B17/00 ,  H04J3/00 ,  H04L5/14 ,  H04B7/26

CPC classification number: H04W52/52 ,  H03G3/3078 ,  H03M1/185 ,  H04B17/318 ,  H04L5/1484

Abstract: A method and system for automatic gain control (AGC) in a TDD communication system, wherein each time slot of the communication signal contains a preamble in binary phase shift keying (BPSK) format, located at the beginning of the time slot. The channel estimation by the receiver is improved since the preamble allows AGC to quickly estimate the signal strength and adjust the gain accordingly. This permits all data symbols within the data burst, which follows the preamble, to be correctly received, and results in a midamble channel estimate that is much more accurate. It also allows the AGC circuit within the TDD receiver to be greatly simplified.

Abstract translation: 一种用于TDD通信系统中的自动增益控制（AGC）的方法和系统，其中通信信号的每个时隙包含位于时隙开头的二进制相移键控（BPSK）格式的前导码。 由于前同步码允许AGC快速估计信号强度并相应地调整增益，所以改善了接收机的信道估计。 这允许正确地接收跟随前导码的数据突发内的所有数据符号，并且导致更准确的中间码信道估计。 它还允许TDD接收机内的AGC电路大大简化。

公开(公告)号：WO03046391A2

公开(公告)日：2003-06-05

申请号：PCT/US0237150

申请日：2002-11-19

Applicant: INTERDIGITAL TECH CORP

Inventor： GREDONE JOSEPH ,  STUFFLET ALFRED ,  AXNESS TIMOTHY A

IPC: H04L29/00 ,  F16B20060101 ,  G06F13/00 ,  G06F13/14 ,  G06F13/38 ,  G06F13/40 ,  H03M9/00 ,  H04Q7/36 ,  F16B

CPC classification number: G06F13/4009

Abstract: A hybrid serial/parallel bus interface for a base station has a data block demultiplexing device. The data block demultiplexing device has an input configured to receive a data block and demultiplexes the data block into a plurality of nibbles. For each nibble, a parallel to serial converter converts the nibble into serial data. A line transfers each nibble's serial data. A serial to parallel converter converts each nibble's serial data to recover that nibble. A data block reconstruction device combines the recovered nibbles into the data block.

Abstract translation: 用于基站的混合串行/并行总线接口具有数据块解复用装置。 数据块解复用装置具有被配置为接收数据块并将数据块解复用为多个半字节的输入。 对于每个半字节，并行到串行转换器将半字节转换为串行数据。 一行传输每个半字节的串行数据。 串行到并行转换器转换每个半字节的串行数据以恢复该半字节。 数据块重建装置将恢复的半字节组合到数据块中。

公开(公告)号：WO2004084460A3

公开(公告)日：2004-12-16

申请号：PCT/US2004007496

申请日：2004-03-12

Applicant: INTERDIGITAL TECH CORP ,  HAIM JOHN W ,  TYRA FRYDERYK ,  GUCCIONE LOUIS J ,  AXNESS TIMOTHY A ,  GRIECO DONALD M

Inventor： HAIM JOHN W ,  TYRA FRYDERYK ,  GUCCIONE LOUIS J ,  AXNESS TIMOTHY A ,  GRIECO DONALD M

IPC: H03G3/00 ,  H03G3/20 ,  H03G3/30 ,  H04B7/005 ,  H04J3/00

CPC classification number: H04W52/52 ,  H03G3/001 ,  H03G3/3052 ,  H03G3/3078

Abstract: An automatic gain control (AGC) method according to the present invention applies an initial gain by a digital AGC circuit (13) in a timeslot is determined using a final calculated gain from the same timeslot in the previous frame together with an offset factor. An erase function (14) is activated for a given data sample block when the number of saturated data samples that are detected within the block (17) exceeds a threshold value. The power measurement made by the AGC circuit and used to update the gain is adjusted based on the number of measured data samples that are saturated. These elements provide a gain limiting function and allows limiting of the dynamic range for further signal processing.

Abstract translation: 根据本发明的自动增益控制（AGC）方法，利用来自前一帧的相同时隙的最终计算的增益以及偏移因子来确定时隙中的数字AGC电路（13）的初始增益。 当在块（17）内检测到的饱和数据样本的数量超过阈值时，针对给定数据采样块激活擦除功能（14）。 由AGC电路进行的用于更新增益的功率测量基于饱和的测量数据样本的数量进行调整。 这些元件提供增益限制功能，并允许限制用于进一步信号处理的动态范围。

公开(公告)号：WO2005076847A3

公开(公告)日：2006-11-30

申请号：PCT/US2005002913

申请日：2005-01-31

Applicant: INTERDIGITAL TECH CORP ,  IACONO ANA LUCIA ,  STERN-BERKOWITZ JANET ,  AXNESS TIMOTHY A ,  ZANGI KAMBIZ CASEY

Inventor： IACONO ANA LUCIA ,  STERN-BERKOWITZ JANET ,  AXNESS TIMOTHY A ,  ZANGI KAMBIZ CASEY

IPC: H04B7/00 ,  H03C7/02 ,  H04W52/42

CPC classification number: H01Q3/24 ,  H04W52/42

Abstract: A method and apparatus for transmit power control (TPC) while switching a beam among a plurality of beams in a wireless communication system. An antenna array generates a plurality of directional beams and preferably an omni-directional pattern and switches a beam among the plurality of beams preferably including the omni-directional pattern. Link quality on at least one of the plurality of beams is measured, and a beam having a greatest link quality is selected. If the selected beam is different from a current beam, a beam is switched from the current beam to the selected beam. While switching a beam, TPC parameters are adjusted based on the link quality difference between the link quality of the current beam and the link quality of the selected beam, and optionally, base on other parameters.

Abstract translation: 一种用于在无线通信系统中切换多个波束之间的波束的发射功率控制（TPC）的方法和装置。 天线阵列产生多个定向波束并且优选地是全向图案，并且在多个波束之间切换优选包括全向图案的波束。 测量多个光束中的至少一个的链路质量，并且选择具有最大链路质量的光束。 如果所选择的光束与当前光束不同，则将光束从当前光束切换到所选择的光束。 在切换波束时，基于当前波束的链路质量与所选波束的链路质量之间的链路质量差，并且可选地，基于其他参数来调整TPC参数。

公开(公告)号：EP1634464A4

公开(公告)日：2008-08-13

申请号：EP04776082

申请日：2004-05-21

Applicant: INTERDIGITAL TECH CORP

Inventor： AXNESS TIMOTHY A ,  KAZAKEVICH LEONID

IPC: H04Q1/00 ,  H04B1/00 ,  H04B1/10 ,  H04B1/44 ,  H04Q20060101

CPC classification number: H04B1/0057 ,  H04B1/525

Abstract: A multi-mode wireless transmit/receive unit (WTRU) includes at least one antenna, first and second communication mode receivers and a first communication mode transmitter. The first and second receivers simultaneously receive signals from the antenna. The first transmitter generates and sends a first type of signal to the antenna while, at the same time, the second receiver receives a second type of signal from the antenna. In a preferred embodiment, the WTRU further includes a vector multiplier configured to reduce or eliminate interference of signals received by the second receiver, the interference being caused by the first transmitter. The vector multiplier adjusts the phase and amplitude of noise (i.e., spurious in-band noise) measured by the second receiver. The WTRU may further include a second communication mode transmitter configured to generate and send a second type of signal to the antenna.

公开(公告)号：EP1456957A4

公开(公告)日：2005-06-15

申请号：EP02784511

申请日：2002-11-19

Applicant: INTERDIGITAL TECH CORP

Inventor： GREDONE JOSEPH ,  STUFFLET ALFRED ,  AXNESS TIMOTHY A

IPC: G06F13/38 ,  G06F13/00 ,  G06F13/14 ,  H03M9/00 ,  H04L25/14

CPC classification number: H04L25/14 ,  H03M9/00

Abstract: A hybrid serial/parallel bus interface has a data block demultiplexing device 40. The data block demultiplexing device 40 has an input configured to receive a data block and demultiplexes the data block into a plurality of nibbles 422. For each nibble, a parallel to serial converter 42i converts the nibble into serial data. A line transfers each nibble's serial data. A serial to parallel converter 46i converts each nibble's serial data to recover that nibble. A data block reconstruction device 48 combines the recovered nibbles into the data block.

公开(公告)号：EP1446723A4

公开(公告)日：2005-04-27

申请号：EP02803987

申请日：2002-11-18

Applicant: INTERDIGITAL TECH CORP

Inventor： GREDONE JOSEPH ,  STUFFLET ALFRED ,  AXNESS TIMOTHY A

IPC: G06F13/38 ,  G11C7/10 ,  G11C8/00 ,  H01Q11/12 ,  H03M9/00 ,  H04B1/04 ,  H04L25/14 ,  H04L29/00 ,  G06F13/00

CPC classification number: G11C7/1006 ,  G11C7/1033 ,  G11C2207/107 ,  H03M9/00 ,  H04L25/14

Abstract: A hybrid serial/parallel bus interface method for a base station has a data block demultiplexing device (40). The data block demultiplexing device has an input configured to receive a data block and demultiplexes the data block into a plurality of nibbles. For each nibble, a parallel to serial converter (42) converts the nibble into serial data. A line (44) transfers each nibble's serial data. A serial to parallel converter (46) converts each nibble's serial data to recover that nibble. A data block reconstruction device (48) combines the recovered nibbles into the data block.

公开(公告)号：EP1446722A4

公开(公告)日：2005-04-20

申请号：EP02789726

申请日：2002-11-18

Applicant: INTERDIGITAL TECH CORP

Inventor： GREDONE JOSEPH ,  STUFFLET ALFRED ,  AXNESS TIMOTHY A

IPC: G06F13/38 ,  H03M9/00 ,  H04L25/14 ,  H04L29/00 ,  G06F13/00

CPC classification number: H03M9/00 ,  H04L25/14

Abstract: A hybrid serial/parallel bus interface for a user equipment (UE) has a data block demultiplexing device (40). The data block demultiplexing device has an input configured to receive a data block and demultiplexes the data block into a plurality of nibbles. For each nibble, a parallel to serial converter (42) converts the nibble into serial data. A line (44) transfers each nibble's serial data. A serial to parallel converter (46) converts each nibble's serial data to recover that nibble. A data block reconstruction device (48) combines the recovered nibbles into the data block.

公开(公告)号：EP1604472A4

公开(公告)日：2007-01-31

申请号：EP04720334

申请日：2004-03-12

Applicant: INTERDIGITAL TECH CORP

Inventor： HAIM JOHN W ,  TYRA FRYDERYK ,  GUCCIONE LOUIS J ,  AXNESS TIMOTHY A ,  GRIECO DONALD M

IPC: H03G3/00 ,  H03G3/20 ,  H03G3/30 ,  H04B7/005 ,  H04J3/00

CPC classification number: H04W52/52 ,  H03G3/001 ,  H03G3/3052 ,  H03G3/3078

Abstract: An automatic gain control (AGC) method according to the present invention applies an initial gain by a digital AGC circuit (13) in a timeslot is determined using a final calculated gain from the same timeslot in the previous frame together with an offset factor. An erase function (14) is activated for a given data sample block when the number of saturated data samples that are detected within the block (17) exceeds a threshold value. The power measurement made by the AGC circuit and used to update the gain is adjusted based on the number of measured data samples that are saturated. These elements provide a gain limiting function and allows limiting of the dynamic range for further signal processing.

公开(公告)号：EP1446887A4

公开(公告)日：2005-05-04

申请号：EP02804002

申请日：2002-11-19

Applicant: INTERDIGITAL TECH CORP

Inventor： GREDONE JOSEPH ,  STUFFLET ALFRED ,  AXNESS TIMOTHY A

IPC: G06F13/38 ,  G06F5/00 ,  H03M9/00 ,  H04L25/14 ,  G06F13/00

CPC classification number: H03M9/00 ,  H04L25/14

Abstract: A hybrid serial/parallel bus interface method for a user equipment (UE) has a data block demultiplexing device (40). The data block demultiplexing device (40) has an input configured to receive a data block and demultiplexes the data block into a plurality of nibbles (42(2)). For each nibble, a parallel to serial converter (42(i)) converts the nibble into serial data. A line (44) transfers each nibble's serial data. A serial to parallel converter (46i) converts each nibble's serial data to recover that nibble. A data block reconstruction device (48) combines the recovered nibbles into the data block.