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    PROGRAMMABLE RADIO INTERFACE
    1.
    发明申请
    PROGRAMMABLE RADIO INTERFACE 审中-公开
    可编程无线接口

    公开(公告)号：WO2004030228A2

    公开(公告)日：2004-04-08

    申请号：PCT/US0330332

    申请日：2003-09-24

    Applicant: INTERDIGITAL TECH CORP

    Inventor： STUFFLET ALFRED ,  GREDONE JOSEPH W ,  SIMEON RICHARD

    IPC: H04B1/04 ,  H04B

    CPC classification number: H04B1/0475

    Abstract: Through the use of a serial bus processor coupled to memory-mapped registers of a programmable radio interface processor (RIP), the novel radio interface of the present invention overcomes the problem of disparate interfaces between the digital section and the analog section of a wireless communications system. The serial bus processor receives data from a plurality of lookup tables which, in turn, are indexed by data received from the analog section. The serial bus processor then uses data values retrieved from the lookup tables to generate processed control data for controlling the digital module. The lookup tables are programmed with data so to compensate for nonlinearities which may be present in the analog section, but are not accounted for in the digital section.

    Abstract translation: 通过使用耦合到可编程无线接口处理器（RIP）的存储器映射寄存器的串行总线处理器，本发明的新型无线电接口克服了无线通信的数字部分和模拟部分之间不同接口的问题 系统。 串行总线处理器从多个查找表接收数据，这些查找表又由从模拟部分接收的数据进行索引。 然后，串行总线处理器使用从查找表检索的数据值来生成用于控制数字模块的处理后的控制数据。 查找表用数据编程，以补偿可能存在于模拟部分中的非线性，但在数字部分中未考虑。

    BASE STATION HAVING A HYBRID PARALLEL/SERIAL BUS INTERFACE
    2.
    发明申请
    BASE STATION HAVING A HYBRID PARALLEL/SERIAL BUS INTERFACE 审中-公开
    具有混合并联/串行总线接口的基站

    公开(公告)号：WO03046391A2

    公开(公告)日：2003-06-05

    申请号：PCT/US0237150

    申请日：2002-11-19

    Applicant: INTERDIGITAL TECH CORP

    Inventor： GREDONE JOSEPH ,  STUFFLET ALFRED ,  AXNESS TIMOTHY A

    IPC: H04L29/00 ,  F16B20060101 ,  G06F13/00 ,  G06F13/14 ,  G06F13/38 ,  G06F13/40 ,  H03M9/00 ,  H04Q7/36 ,  F16B

    CPC classification number: G06F13/4009

    Abstract: A hybrid serial/parallel bus interface for a base station has a data block demultiplexing device. The data block demultiplexing device has an input configured to receive a data block and demultiplexes the data block into a plurality of nibbles. For each nibble, a parallel to serial converter converts the nibble into serial data. A line transfers each nibble's serial data. A serial to parallel converter converts each nibble's serial data to recover that nibble. A data block reconstruction device combines the recovered nibbles into the data block.

    Abstract translation: 用于基站的混合串行/并行总线接口具有数据块解复用装置。 数据块解复用装置具有被配置为接收数据块并将数据块解复用为多个半字节的输入。 对于每个半字节，并行到串行转换器将半字节转换为串行数据。 一行传输每个半字节的串行数据。 串行到并行转换器转换每个半字节的串行数据以恢复该半字节。 数据块重建装置将恢复的半字节组合到数据块中。

    METHOD OF TRANSFERRING DATA
    4.
    发明公开
    METHOD OF TRANSFERRING DATA 审中-公开
    法传送数据

    公开(公告)号：EP1446887A4

    公开(公告)日：2005-05-04

    申请号：EP02804002

    申请日：2002-11-19

    Applicant: INTERDIGITAL TECH CORP

    Inventor： GREDONE JOSEPH ,  STUFFLET ALFRED ,  AXNESS TIMOTHY A

    IPC: G06F13/38 ,  G06F5/00 ,  H03M9/00 ,  H04L25/14 ,  G06F13/00

    CPC classification number: H03M9/00 ,  H04L25/14

    Abstract: A hybrid serial/parallel bus interface method for a user equipment (UE) has a data block demultiplexing device (40). The data block demultiplexing device (40) has an input configured to receive a data block and demultiplexes the data block into a plurality of nibbles (42(2)). For each nibble, a parallel to serial converter (42(i)) converts the nibble into serial data. A line (44) transfers each nibble's serial data. A serial to parallel converter (46i) converts each nibble's serial data to recover that nibble. A data block reconstruction device (48) combines the recovered nibbles into the data block.

    HYBRID PARALLEL/SERIAL BUS INTERFACE
    5.
    发明公开
    HYBRID PARALLEL/SERIAL BUS INTERFACE 有权
    混合并行串行总线接口

    公开(公告)号：EP1456957A4

    公开(公告)日：2005-06-15

    申请号：EP02784511

    申请日：2002-11-19

    Applicant: INTERDIGITAL TECH CORP

    Inventor： GREDONE JOSEPH ,  STUFFLET ALFRED ,  AXNESS TIMOTHY A

    IPC: G06F13/38 ,  G06F13/00 ,  G06F13/14 ,  H03M9/00 ,  H04L25/14

    CPC classification number: H04L25/14 ,  H03M9/00

    Abstract: A hybrid serial/parallel bus interface has a data block demultiplexing device 40. The data block demultiplexing device 40 has an input configured to receive a data block and demultiplexes the data block into a plurality of nibbles 422. For each nibble, a parallel to serial converter 42i converts the nibble into serial data. A line transfers each nibble's serial data. A serial to parallel converter 46i converts each nibble's serial data to recover that nibble. A data block reconstruction device 48 combines the recovered nibbles into the data block.

    PROGRAMMABLE RADIO INTERFACE
    6.
    发明公开
    PROGRAMMABLE RADIO INTERFACE 有权
    可编程无线电接口

    公开(公告)号：EP1547261A4

    公开(公告)日：2005-12-21

    申请号：EP03777533

    申请日：2003-09-24

    Applicant: INTERDIGITAL TECH CORP

    Inventor： STUFFLET ALFRED ,  GREDONE JOSEPH W ,  SIMEON RICHARD

    IPC: H04B1/04 ,  H04B1/40 ,  H03K9/00 ,  H04B1/38 ,  H04L27/06 ,  H04M1/00

    CPC classification number: H04B1/0475

    Abstract: Through the use of a serial bus processor (120) coupled to memory-mapped registers of a programmable radio interface processor (107), the novel radio interface of the present invention overcomes the problem of disparate interfaces between the digital section (136) and the analog section (138) of a wireless communications system. The serial bus processor receives data from a plurality of lookup tables (127) which, in turn, are indexed by data received from the analog section. The serial bus processor then uses data values retrieved from lookup tables to generate processed control data for controlling the digital module. The lookup tables are programmed with data so to compensate for nonlinearities which may be present in the analog section, but are not accounted for in the digital section.

    USER EQUIPMENT (UE) HAVING A HYBRID PARALLEL/SERIAL BUS INTERFACE
    8.
    发明公开
    USER EQUIPMENT (UE) HAVING A HYBRID PARALLEL/SERIAL BUS INTERFACE 审中-公开
    使用混合并行/串行总线接口的用户设备（UE）

    公开(公告)号：EP1446722A4

    公开(公告)日：2005-04-20

    申请号：EP02789726

    申请日：2002-11-18

    Applicant: INTERDIGITAL TECH CORP

    Inventor： GREDONE JOSEPH ,  STUFFLET ALFRED ,  AXNESS TIMOTHY A

    IPC: G06F13/38 ,  H03M9/00 ,  H04L25/14 ,  H04L29/00 ,  G06F13/00

    CPC classification number: H03M9/00 ,  H04L25/14

    Abstract: A hybrid serial/parallel bus interface for a user equipment (UE) has a data block demultiplexing device (40). The data block demultiplexing device has an input configured to receive a data block and demultiplexes the data block into a plurality of nibbles. For each nibble, a parallel to serial converter (42) converts the nibble into serial data. A line (44) transfers each nibble's serial data. A serial to parallel converter (46) converts each nibble's serial data to recover that nibble. A data block reconstruction device (48) combines the recovered nibbles into the data block.

    INTERFAZ DE RADIO PROGRAMABLE.
    9.
    发明专利
    INTERFAZ DE RADIO PROGRAMABLE. 未知

    公开(公告)号：ES2304535T3

    公开(公告)日：2008-10-16

    申请号：ES03777533

    申请日：2003-09-24

    Applicant: INTERDIGITAL TECH CORP

    Inventor： STUFFLET ALFRED ,  GREDONE JOSEPH W ,  SIMEON RICHARD

    IPC: H04B1/40 ,  H03K9/00 ,  H04B1/04 ,  H04B1/38 ,  H04L27/06 ,  H04M1/00

    Abstract: Un método para establecer una interfaz de cualquiera de una pluralidad de módulos de radio analógicos con un módulo digital en un sistema que comprende (i) un procesador de barra de distribución en serie (120), (ii) un procesador de interfaz de radio programable (RIP) (127) que incluye uno o más registros en configuración de memoria (133) acoplados al procesador de barra de distribución en serie, y (iii) una pluralidad de tablas de búsqueda (101, 103, 105), estando el método caracterizado por los pasos de: (a) programar la pluralidad de tablas de búsqueda con datos para compensar una o más no linealidades que pueden estar presentes en uno de la pluralidad de módulos de radio analógicos (138), pero no son tenidas en cuenta en el módulo digital; (b) indexar la pluralidad de tablas de búsqueda usando los datos recibidos de un módulo de radio digital (196); (c) recibir el procesador de barra de distribución en serie datos de la pluralidad de tablas de búsqueda; y (d) el procesador de barra de distribución en serie que usa valores recuperados de las tablas de búsqueda para generar datos procesados para controlar uno de la pluralidad de módulos de radio analógicos, en los que el establecimiento de la interfaz con otro de una pluralidad de módulos de radio analógicos es por una reconfiguración del soporte lógico.

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