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公开(公告)号:US20210240252A1
公开(公告)日:2021-08-05
申请号:US17234681
申请日:2021-04-19
Applicant: Intel Corporation
Inventor: Ren Wang , Christian Maciocco , Sanjay Bakshi , Tsung-Yuan Charles Tai
IPC: G06F1/3287 , G06F1/329 , G06F1/3203 , G06F9/4401
Abstract: The present invention relates to platform power management.
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公开(公告)号:US10817425B2
公开(公告)日:2020-10-27
申请号:US14583389
申请日:2014-12-26
Applicant: Intel Corporation
Inventor: Ren Wang , Andrew J. Herdrich , Yen-cheng Liu , Herbert H. Hum , Jong Soo Park , Christopher J. Hughes , Namakkal N. Venkatesan , Adrian C. Moga , Aamer Jaleel , Zeshan A. Chishti , Mesut A. Ergin , Jr-shian Tsai , Alexander W. Min , Tsung-yuan C. Tai , Christian Maciocco , Rajesh Sankaran
IPC: G06F12/0842 , G06F12/0831 , G06F12/0893 , G06F12/109 , G06F12/0813 , G06F9/455
Abstract: Methods and apparatus implementing Hardware/Software co-optimization to improve performance and energy for inter-VM communication for NFVs and other producer-consumer workloads. The apparatus include multi-core processors with multi-level cache hierarchies including and L1 and L2 cache for each core and a shared last-level cache (LLC). One or more machine-level instructions are provided for proactively demoting cachelines from lower cache levels to higher cache levels, including demoting cachelines from L1/L2 caches to an LLC. Techniques are also provided for implementing hardware/software co-optimization in multi-socket NUMA architecture system, wherein cachelines may be selectively demoted and pushed to an LLC in a remote socket. In addition, techniques are disclosure for implementing early snooping in multi-socket systems to reduce latency when accessing cachelines on remote sockets.
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公开(公告)号:US20200074047A1
公开(公告)日:2020-03-05
申请号:US16373300
申请日:2019-04-02
Applicant: Intel Corporation
Inventor: Malini K. Bhandaru , Kapil Sood , Christian Maciocco , Isaku Yamahata , Yunhong Jiang
IPC: G06F21/10
Abstract: At least one machine readable medium comprising a plurality of instructions that in response to being executed by a system cause the system to send a unique identifier to a license server, establish a secure channel based on the unique identifier, request a license for activating an appliance from a license server over the secure channel, receive license data from the license server over the secure channel; determine whether the license is valid, and activate the appliance in response to a determination that the license data is valid.
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公开(公告)号:US10284470B2
公开(公告)日:2019-05-07
申请号:US14580801
申请日:2014-12-23
Applicant: Intel Corporation
Inventor: Ren Wang , Namakkal N. Venkatesan , Aamer Jaleel , Tsung-Yuan C. Tai , Sameh Gobriel , Christian Maciocco
IPC: H04L12/743 , H04L29/06 , H04L12/747
Abstract: Technologies for managing network flow lookups of a network device include a network controller and a target device, each communicatively coupled to the network device. The network device includes a cache for a processor of the network device and a main memory. The network device additionally includes a multi-level hash table having a first-level hash table stored in the cache of the network device and a second-level hash table stored in the main memory of the network device. The network device is configured to determine whether to store a network flow hash corresponding to a network flow indicating the target device in the first-level or second-level hash table based on a priority of the network flow provided to the network device by the network controller.
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公开(公告)号:US20190104150A1
公开(公告)日:2019-04-04
申请号:US15720821
申请日:2017-09-29
Applicant: Intel Corporation
Inventor: Sameh Gobriel , Christian Maciocco , Byron Marohn , Ren Wang , Tsung-Yuan C. Tai
Abstract: A computing apparatus for providing a node within a distributed network function, including: a hardware platform; a network interface to communicatively couple to at least one other peer node of the distributed network function; a distributor function including logic to operate on the hardware platform, including a hashing module configured to receive an incoming network packet via the network interface and perform on the incoming network packet a first-level hash of a two-level hash, the first level hash being a lightweight hash with respect to a second-level hash, the first level hash to deterministically direct a packet to one of the nodes of the distributed network function as a directed packet; and a denial of service (DoS) mitigation engine to receive notification of a DoS attack, identify a DoS packet via the first-level hash, and prevent the DoS packet from reaching the second-level hash.
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公开(公告)号:US20180337850A1
公开(公告)日:2018-11-22
申请号:US15845107
申请日:2017-12-18
Applicant: Intel Corporation
Inventor: Nrupal Jani , Dinesh Kumar , Christian Maciocco , Ren Wang , Neerav Parikh , John Fastabend , Iosif Gasparakis , David J. Harriman , Patrick L. Connor , Sanjeev Jain
IPC: H04L12/721 , H04L12/911 , H04L12/803 , H04L12/725 , H04L12/26
CPC classification number: H04L45/44 , H04L43/026 , H04L43/0817 , H04L43/0876 , H04L43/16 , H04L45/306 , H04L47/125 , H04L47/781
Abstract: Devices and techniques for hardware accelerated packet processing are described herein. A device can communicate with one or more hardware switches. The device can detect characteristics of a plurality of packet streams. The device may distribute the plurality of packet streams between the one or more hardware switches and software data plane components based on the detected characteristics of the plurality of packet streams, such that at least one packet stream is designated to be processed by the one or more hardware switches. Other embodiments are also described.
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公开(公告)号:US20180225136A1
公开(公告)日:2018-08-09
申请号:US15812888
申请日:2017-11-14
Applicant: INTEL CORPORATION
Inventor: Ashok Sunder Rajan , Richard A. Uhlig , Rajendra S. Yavatkar , Tsung-Yuan C. Tai , Christian Maciocco , Jeffrey R. Jackson , Daniel J. Dahle
Abstract: In the present disclosure, functions associated with the central office of an evolved packet core network are co-located onto a computer platform or sub-components through virtualized function instances. This reduces and/or eliminates the physical interfaces between equipment and permits functional operation of the evolved packet core to occur at a network edge.
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公开(公告)号:US20180019943A1
公开(公告)日:2018-01-18
申请号:US15717287
申请日:2017-09-27
Applicant: Intel Corporation
Inventor: Sameh Gobriel , Ren Wang , Christian Maciocco , Tsung-Yuan Tai
IPC: H04L12/721 , H04L12/755 , H04L12/743 , H04L12/751 , H04L12/725
CPC classification number: H04L45/44 , H04L45/02 , H04L45/021 , H04L45/306 , H04L45/7453
Abstract: Technologies for distributed table lookup via a distributed router includes an ingress computing node, an intermediate computing node, and an egress computing node. Each computing node of the distributed router includes a forwarding table to store a different set of network routing entries obtained from a routing table of the distributed router. The ingress computing node generates a hash key based on the destination address included in a received network packet. The hash key identifies the intermediate computing node of the distributed router that stores the forwarding table that includes a network routing entry corresponding to the destination address. The ingress computing node forwards the received network packet to the intermediate computing node for routing. The intermediate computing node receives the forwarded network packet, determines a destination address of the network packet, and determines the egress computing node for transmission of the network packet from the distributed router.
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公开(公告)号:US20160378170A1
公开(公告)日:2016-12-29
申请号:US15195485
申请日:2016-06-28
Applicant: INTEL CORPORATION
Inventor: Ren Wang , Christian Maciocco , Sanjay Bakshi , Tsung-Yuan Charles Tai
CPC classification number: G06F1/3287 , G06F1/3203 , G06F1/329 , G06F9/4418 , Y02D10/24 , Y02D50/20
Abstract: The present invention relates to platform power management.
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公开(公告)号:US09390010B2
公开(公告)日:2016-07-12
申请号:US13715526
申请日:2012-12-14
Applicant: Intel Corporation
Inventor: Ahmad Samih , Ren Wang , Christian Maciocco , Sameh Gobriel , Tsung-Yuan Tai
IPC: G06F12/08
CPC classification number: G06F12/0804 , G06F12/0888 , Y02D10/13
Abstract: The present disclosure provides techniques for cache management. A data block may be received from an IO interface. After receiving the data block, the occupancy level of a cache memory may be determined. The data block may be directed to a main memory if the occupancy level exceeds a threshold. The data block may be directed to a cache memory if the occupancy level is below a threshold.
Abstract translation: 本公开提供了用于高速缓存管理的技术。 可以从IO接口接收数据块。 在接收到数据块之后,可以确定高速缓冲存储器的占用水平。 如果占用率超过阈值,则数据块可以被引导到主存储器。 如果占用水平低于阈值,则数据块可以被引导到高速缓冲存储器。
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