公开(公告)号：WO1996041380A1

公开(公告)日：1996-12-19

申请号：PCT/US1996009056

申请日：1996-06-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  HARSHFIELD, Steven, T.

IPC: H01L27/24

CPC classification number: H01L27/24

Abstract: A memory device having a plurality of memory arrays. Each array has a plurality of memory cells, each memory cell including an electrode defining a respective contact area. Each memory array is formed by depositing a continuous chalcogenide layer. This chalcogenide layer, even when continuous, will have active areas formed above the electrodes, and a conductive layer electrically coupling at least a portion of the active areas. The memory array can also include a dielectric volume surrounding at least a portion of the plurality of electrodes. The electrodes can be contacts, plugs or pillars deposited in etched openings in the dielectric volume.

Abstract translation: 一种具有多个存储器阵列的存储器件。 每个阵列具有多个存储单元，每个存储单元包括限定相应接触区域的电极。 通过沉积连续的硫族化物层形成每个存储器阵列。 该硫族化物层即使在连续的情况下也将具有形成在电极上方的有源区，并且导电层电耦合至少一部分有源区。 存储器阵列还可以包括围绕多个电极的至少一部分的介电体积。 电极可以是沉积在介电体积中的蚀刻开口中的触点，插塞或柱。

公开(公告)号：WO1996039698A1

公开(公告)日：1996-12-12

申请号：PCT/US1996009070

申请日：1996-06-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  SEYYEDY, Mirmajid

IPC: G11C11/407

CPC classification number: G11C11/4074 ,  G11C11/4094

Abstract: An integrated circuit dynamic memory device is described which stores data in memory cells as a charge on a capacitor. The memory cells have a common cell plate and can be selectively connected to a digit line. Sensing circuitry, including both p-sense and n-sense amplifiers, is connected to the digit line and the cell plate. Equalization circuitry is described to equalize the cell plate and digit line for sensing data stored on a memory cell. Isolation circuitry is described for selectively isolating the sensing circuitry from the memory cells.

Abstract translation: 描述了将存储器单元中的数据作为电容器上的电荷存储的集成电路动态存储器件。 存储单元具有公共单元板，并且可以选择性地连接到数字线。 感测电路，包括p感测放大器和n读出放大器，连接到数字线和单元板。 描述均衡电路以均衡用于感测存储在存储单元上的数据的单元板和数字线。 描述了用于选择性地将感测电路与存储器单元隔离的隔离电路。

公开(公告)号：WO1996036052A2

公开(公告)日：1996-11-14

申请号：PCT/US1996006709

申请日：1996-05-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  MCLAURY, Loren, L.

IPC: G11C11/00

CPC classification number: G11C7/1078 ,  G11C7/1033 ,  G11C7/1075

Abstract: An integrated circuit memory is described which has a multi-bit write register. Each plane of the multi-bit write register has a plurality of bits, or columns. The multi-bit write register allows each memory cell in a block of selected memory cells of the integrated circuit memory to be block written to a different logic state. The write register can be a color register in a multi-port memory device, or a single port device. Several methods of loading the write register are also described. These methods include loading the write register one column at a time or one plane at a time. The columns or planes can be loaded in either a pre-determined pattern, or selectively loaded.

Abstract translation: 描述了具有多位写寄存器的集成电路存储器。 多位写寄存器的每个平面具有多个位或列。 多位写寄存器允许将集成电路存储器的选定存储单元的块中的每个存储单元写入不同的逻辑状态。 写入寄存器可以是多端口存储器设备中的颜色寄存器，也可以是单端口设备。 还描述了加载写入寄存器的几种方法。 这些方法包括一次加载写入寄存器一列或一个平面。 列或平面可以以预定图案或有选择地装载。

公开(公告)号：WO1996027902A1

公开(公告)日：1996-09-12

申请号：PCT/US1996002859

申请日：1996-02-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  BLALOCK, Guy, T. ,  HOWARD, Bradley, J.

IPC: H01L21/8242

CPC classification number: H01L27/10852 ,  H01L27/10817 ,  H01L28/82 ,  H01L28/84 ,  H01L28/90 ,  Y10S438/948

Abstract: A method of forming a stacked container capacitor includes, a) providing a substrate having a node (14) to which electrical connection to a capacitor is to be made; b) then, providing a layer of photoresist (20); c) patterning the photoresist to form a photoresist contact (22) which overlaps within lateral confines of the node, and in a manner which produces inner photoresist contact sidewalls having standing wave ripples; d) providing a layer of sacrificial material (28) over the photoresist and within the photoresist contact, the sacrificial layer having a thickness which less than completely fills the photoresist contact, the standing wave ripples first transferring to those regions of the sacrificial layer which overlap the photoresist contact inner sidewall standing wave ripples; e) anisotropically etching the sacrificial material to produce a male molding ring (32) having outer sidewalls possessing the first transferred standing wave ripples; f) stripping the photoresist; g) providing a layer of electrically conductive material (36) over and within the male molding ring, the first transferred standing wave ripples second transferring to those regions of the conductive layer which overlap the first transferred standing wave ripples; h) anisotropically etching the conductive layer to outwardly expose upper portions of the male molding ring and produce a capacitor container ring (40) having inner sidewalls possessing the second transferred standing wave ripples, the capacitor container ring electrically contacting the node; i) stripping the male molding ring from the substrate; and j) providing a capacitor dielectric layer (46) and outer capacitor plate (48) over the capacitor container rippled inner sidewalls.

Abstract translation: 形成堆叠式容器电容器的方法包括：a）提供具有与电容器进行电连接的节点（14）的衬底; b）然后，提供一层光致抗蚀剂（20）; c）图案化光致抗蚀剂以形成在节点的横向边界内重叠的光致抗蚀剂接触（22），并且以产生具有驻波波纹的内部光致抗蚀剂接触侧壁的方式; d）在光致抗蚀剂和光致抗蚀剂接触物之内提供一层牺牲材料（28），牺牲层具有小于完全填充光致抗蚀剂接触的厚度，驻波波纹首先转移到重叠的牺牲层的那些区域 光刻胶接触内侧壁驻波波纹; e）各向异性蚀刻所述牺牲材料以产生具有外侧壁的阳模制环（32），所述外侧壁具有所述第一转移的驻波波纹; f）剥离光致抗蚀剂; g）在阳模制环之上和之内提供一层导电材料（36），第一转移的驻波波纹第二次转移到与第一转移的驻波波纹重叠的导电层的那些区域; h）各向异性蚀刻所述导电层以向外暴露所述阳模制环的上部并产生具有内侧壁的电容器容器环（40），所述电容器容器环具有所述第二传递的驻波波纹，所述电容器容器环与所述节点电接触; i）从基材剥离阳模塑环; 以及j）在电容器容器波纹的内侧壁上方提供电容器介电层（46）和外部电容器板（48）。

公开(公告)号：WO1996027901A1

公开(公告)日：1996-09-12

申请号：PCT/US1996003074

申请日：1996-03-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  RHODES, Howard, E.

IPC: H01L21/768

CPC classification number: H01L27/10894 ,  H01L21/76805 ,  H01L21/76838 ,  H01L23/485 ,  H01L23/5226 ,  H01L27/10808 ,  H01L27/10811 ,  H01L27/10882 ,  H01L27/10888 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device and fabrication process wherein the device includes a conductive layer with a localized thick region positioned below the contact hole. In one embodiment of the invention, the thick region to which contact is made is formed by means of an opening in an underlayer of material. This embodiment of the device includes an underlayer of material (20) having an opening (24) therein; a layer of thin conductive material (26) formed on the underlayer and in the opening; an overlayer of material (28) having a contact hole (30) therethrough formed on the layer of thin conductive material; a conductor (32) contacting the layer of thin conductive material through the contact hole; and wherein the opening (24) in the underlayer is positioned below the contact hole (30) and sized and shaped to form a localized thick region (34) in the layer of thin conductive material within the opening.

Abstract translation: 一种半导体器件和制造工艺，其中所述器件包括具有位于所述接触孔下方的局部厚区域的导电层。 在本发明的一个实施例中，通过材料底层中的开口形成接触的厚区域。 该装置的该实施例包括其中具有开口（24）的材料（20）的底层; 形成在底层和开口中的薄导电材料层（26）; 具有穿过其形成在薄导电材料层上的接触孔（30）的材料（28）的覆盖层; 导体（32），其通过所述接触孔与所述薄导电材料层接触; 并且其中所述底层中的所述开口（24）位于所述接触孔（30）的下方并且其尺寸和形状以在所述开口内的所述薄导电材料层中形成局部厚区域（34）。

公开(公告)号：WO1996026542A1

公开(公告)日：1996-08-29

申请号：PCT/US1996000929

申请日：1996-01-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  MATHEWS, Viju, K. ,  JENG, Nanseng ,  FAZAN, Pierre, C.

IPC: H01L23/522

CPC classification number: H01L21/76843 ,  H01L21/76804 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor processing method of forming an electrically conductive contact plug relative to a wafer includes: a) providing a substrate (36) to which electrical connection is to be made; b) depositing a layer of first material (40) atop the substrate (36) to a selected thickness; c) pattern masking the first material layer (40) for formation of a desired contact opening (44) therethrough; d) etching through the first material layer (40) to form a contact opening (44) therethrough for making electrical connection with the substrate, the contact opening having an outermost region; e) after etching to form the contact opening (44), removing the masking (42) from the first material layer; f) after removing the masking (42) from the first material layer (40), facet sputter etching into the first material layer (40) relative to the contact opening (44) to provide outwardly angled sidewalls (48) which effectively widen the contact opening outermost region, the outwardly angled sidewalls (48) having an inner base where they join with the original contact opening (44); g) depositing a layer of conductive material (52) atop the wafer and to within the facet etched contact opening to fill the contact opening (44); and h) etching the conductive material (52) and first material layer (40) inwardly to at least the angled sidewalls' inner base to define an electrically conductive contact plug which electrically connects with the substrate (36).

Abstract translation: 相对于晶片形成导电接触插塞的半导体处理方法包括：a）提供要进行电连接的衬底（36）; b）在衬底（36）的顶部上沉积一层第一材料（40）至所选择的厚度; c）图案掩蔽所述第一材料层（40）以形成通过其中的期望的接触开口（44）; d）通过第一材料层（40）蚀刻以形成通过其与基板电连接的接触开口（44），所述接触开口具有最外区域; e）在蚀刻之后形成接触开口（44），从第一材料层去除掩模（42）; f）在从第一材料层（40）去除掩模（42）之后，相对于接触开口（44）将溅射刻蚀成第一材料层（40），从而提供向外成角度的侧壁（48），从而有效地使接触 开口的最外区域，向外成角度的侧壁（48）具有内基座，在其中它们与原始接触开口（44）连接; g）在所述晶片顶部和所述刻面蚀刻的接触开口内沉积导电材料层（52）以填充所述接触开口（44）; 以及h）将所述导电材料（52）和第一材料层（40）向内蚀刻到至少所述成角度的侧壁的内部基部，以限定与所述衬底（36）电连接的导电接触插塞。

公开(公告)号：WO1996025761A1

公开(公告)日：1996-08-22

申请号：PCT/US1996001772

申请日：1996-02-09

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  ROBERTS, Martin, Cederiq ,  TANG, Sanh, D.

IPC: H01L21/74

CPC classification number: H01L27/10882 ,  H01L21/76838 ,  H01L23/485 ,  H01L27/11 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming an electrical interconnect overlying a buried contact region (40) of a susbtrate (15) is characterized by a deposition of a first polycrystalline silicon layer (20) and the patterning and etching of same to form a via (41). The via (41) is formed in the first polycrystalline silicon layer (20) to expose the substrate (15) and a second polycrystalline silicon layer (45) is formed in the via to contact the substrate (15). Portions of the second polycrystalline silicon layer (45) overlying the first polycrystalline silicon layer (20) are removed eliminating any horizontal interface between the two polycrystalline silicon layers (20, 45). The first polycrystalline silicon layer (20) remaining after the etch is then patterned to form an electrical interconnect (55).

Abstract translation: 一种用于形成覆盖在所述掩模接触区域（40）上的电互连的方法的特征在于沉积第一多晶硅层（20）并进行图案化和蚀刻以形成通孔（41）。 通孔（41）形成在第一多晶硅层（20）中以暴露衬底（15），并且在通孔中形成第二多晶硅层（45）以接触衬底（15）。 除去覆盖在第一多晶硅层（20）上的第二多晶硅层（45）的部分，消除了两个多晶硅层（20,45）之间的任何水平界面。 然后在蚀刻之后残留的第一多晶硅层（20）被图案化以形成电互连（55）。

公开(公告)号：WO1996014660A1

公开(公告)日：1996-05-17

申请号：PCT/US1995014483

申请日：1995-11-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  AKRAM, Salman ,  FARNWORTH, Warren, M. ,  WOOD, Alan, G.

IPC: H01L21/66

CPC classification number: G01R1/06738 ,  G01R1/07314 ,  H01L2224/13019 ,  H05K1/0306 ,  H05K3/325 ,  H05K2201/0367 ,  H05K2201/0373 ,  H05K2201/09045 ,  Y10T29/49155 ,  Y10T29/49453

Abstract: A method for forming a self-limiting, silicon based interconnect for making temporary electrical contact with bond pads on a semiconductor die is provided. The interconnect includes a silicon substrate having an array of contact members adapted to contact the bond pads on the die for test purposes (e.g., burn-in testing). The interconnect is fabricated by: forming the contact members on the substrate; forming a conductive layer on the tip of the contact members; and then forming conductive traces to the conductive layer. The conductive layer is formed by depositing a silicon containing layer (e.g., polysilicon, amorphous silicon) and a metal layer (e.g., titanium, tungsten, platinum) on the substrate and contact members. These layers are reacted to form a silicide. The unreacted metal and silicon containing layer are then etched selective to the conductive layer which remains on the tip of the contact members. Conductive traces are then formed in contact with the conductive layer using a suitable metallization process. Bond wires are attached to the conductive traces and may be attached to external test circuitry. Alternately, another conductive path such as external contacts (e.g., slide contacts) may provide a conductive path between the conductive traces and external circuitry. The conductive layer, conductive traces and bond wires provide a low resistivity conductive path from the tips of the contact members to external test circuitry.

Abstract translation: 提供一种用于形成用于与半导体管芯上的接合焊盘暂时电接触的自限制硅基互连的方法。 互连包括具有适于接触芯片上的接合焊盘的接触部件阵列的硅衬底用于测试目的（例如，老化测试）。 互连通过以下方式制造：在衬底上形成接触构件; 在所述接触构件的尖端上形成导电层; 然后在导电层上形成导电迹线。 通过在衬底和接触构件上沉积含硅层（例如，多晶硅，非晶硅）和金属层（例如，钛，钨，铂）形成导电层。 这些层反应形成硅化物。 然后将未反应的含金属和含硅层选择性地蚀刻到保留在接触构件的尖端上的导电层。 然后使用合适的金属化工艺将导电迹线形成为与导电层接触。 接合线连接到导电迹线，并且可以附接到外部测试电路。 或者，诸如外部触点（例如，滑动触点）的另一导电路径可以在导电迹线和外部电路之间提供导电路径。 导电层，导电迹线和接合线提供从接触构件的尖端到外部测试电路的低电阻率导电路径。

公开(公告)号：WO1996013003A1

公开(公告)日：1996-05-02

申请号：PCT/US1995013514

申请日：1995-10-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  ZAGAR, Paul, S. ,  KEETH, Brent ,  ONG, Adrian, E.

IPC: G06F11/20

CPC classification number: G11C29/70 ,  G01R31/3004 ,  G06F11/22 ,  G11C11/401 ,  G11C29/02 ,  G11C29/44 ,  G11C29/50 ,  G11C29/83 ,  G11C29/832 ,  G11C29/88 ,  G11C2029/5006

Abstract: An integrated circuit memory device has multiple subarray partitions which can be independently isolated from the remaining circuitry on the integrated circuit. Subarrays of the integrated circuit can be independently tested. Should a subarray of the integrated circuit be found inoperable it is electrically isolated from the remaining circuitry on the integrated circuit so that it cannot interfere with the normal operation of the remaining circuitry. Defects such as power to ground shorts in a subarray which would have previously been catastrophic can be electrically isolated allowing the remaining functional subarrays to be utilized. Integrated circuit repair by isolation of inoperative elements eliminates the current draw and other performance degradations that have previously been associated with integrated circuits with defects repaired through the incorporation of redundant elements alone.

Abstract translation: 集成电路存储器件具有多个子阵列分隔，其可以独立地与集成电路上的剩余电路隔离。 集成电路的子阵列可以独立测试。 如果发现集成电路的子阵列不可操作，则它与集成电路上的剩余电路电隔离，使得其不能干扰剩余电路的正常操作。 以前曾经是灾难性的子阵列中的诸如对地短路的电力的缺陷可以是电隔离的，允许利用剩余的功能子阵列。 通过隔离不起作用元件的集成电路修复消除了以前与集成电路相关的电流消耗和其他性能下降，缺陷通过单独使用冗余元件进行维修。

公开(公告)号：WO1990005377A1

公开(公告)日：1990-05-17

申请号：PCT/US1988003841

申请日：1988-10-31

Applicant: MICRON TECHNOLOGY, INC. ,  LOWREY, Tyler, A.

Inventor： MICRON TECHNOLOGY, INC.

IPC: H01L21/265

CPC classification number: H01L27/10844 ,  H01L21/76202 ,  H01L21/76216 ,  H01L27/105 ,  H01L29/66181 ,  H01L29/94

Abstract: Local Encroachment Reduction (LER) is described, in which a fraction of field oxide is selectively etched. A high energy boron implant is used to maintain adequate active area isolation after the removal. This implant also doubles as an LER high capacitance and provides a carrier to minority substrate electrons. After the high energy boron implant, an N-type bottom plate capacitor is implanted. At that point, the wafer is completed by existing techniques.

Abstract translation: 描述了局部侵蚀减少（LER），其中选择性地蚀刻了一部分场氧化物。 使用高能硼植入物在去除后保持适当的有源面积隔离。 该植入物也兼作LER高电容，并为少数衬底电子提供载体。 在高能量硼注入之后，植入N型底板电容器。 在这一点上，晶圆是通过现有技术完成的。