公开(公告)号：AU2569602A

公开(公告)日：2002-07-01

申请号：AU2569602

申请日：2001-11-19

Applicant: MOTOROLA INC

Inventor： HILT LYNDEE L ,  RAMDANI JAMAL

IPC: H01L21/20 ,  H01L21/314 ,  H01L21/316

公开(公告)号：SG89364A1

公开(公告)日：2002-06-18

申请号：SG200007438

申请日：2000-12-13

Applicant: MOTOROLA INC

Inventor： YU ZHIYI ,  WANG JUN ,  DROOPAD RAVINDRANATH ,  RAMDANI JAMAL

IPC: C30B23/02 ,  H01L21/02 ,  H01L21/20 ,  H01L21/314 ,  H01L21/316 ,  H01L21/318 ,  H01L21/8246 ,  H01L27/105

Abstract: A method for fabricating a semiconductor structure comprises the steps of providing a silicon substrate (10) having a surface (12); forming on the surface of the silicon substrate an interface (14) characterised by a single atomic layer of silicon, nitrogen, and a metal; and forming one or more layers of a single crystal oxide (26) on the interface. The interface comprises an atomic layer of silicon, nitrogen, and a metal in the form MSiN2, where M is a metal. In a second embodiment, the interface comprises an atomic layer of silicon, a metal, and a mixture of nitrogen and oxygen in the form MSiÄN1-xOxÜ2, where M is a metal and X is 0≤X

公开(公告)号：SG85710A1

公开(公告)日：2002-01-15

申请号：SG200003692

申请日：2000-07-03

Applicant: MOTOROLA INC

Inventor： RAMDANI JAMAL ,  DROOPAD RAVINDRANATH ,  YU ZHIYI

IPC: H01L21/02 ,  C30B29/32 ,  H01L21/316 ,  C30B1/00

Abstract: A method for fabricating a semiconductor structure including the steps of providing a silicon substrate (10) having a surface (12); forming amorphous silicon dioxide (14) on the surface (12) of the silicon substrate (10); providing a metal oxide (18) on the amorphous silicon dioxide (14); heating the semiconductor structure to form an interface characterised by a seed layer (20) adjacent the surface (12) of the silicon substrate (10); and forming one or more layers of a high dielectric constant oxide (22) on the seed layer (20).

公开(公告)号：AU3682001A

公开(公告)日：2001-08-20

申请号：AU3682001

申请日：2001-02-08

Applicant: MOTOROLA INC

Inventor： RAMDANI JAMAL ,  DROOPAD RAVINDRANATH ,  HILT LYNDEE L ,  EISENBEISER KURT WILLIAM

IPC: H01L21/331 ,  C30B25/18 ,  H01L21/20 ,  H01L21/205 ,  H01L21/316 ,  H01L21/318 ,  H01L21/822 ,  H01L21/8222 ,  H01L21/8232 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8248 ,  H01L21/8249 ,  H01L21/8252 ,  H01L21/8258 ,  H01L27/04 ,  H01L27/06 ,  H01L27/092 ,  H01L27/095 ,  H01L27/14 ,  H01L27/15 ,  H01L29/26 ,  H01L29/267 ,  H01L29/732 ,  H01L33/16 ,  H01L33/30 ,  H01S5/02 ,  H01S5/026 ,  H01L21/36

Abstract: High quality epitaxial layers of compound semiconductor materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline compound semiconductor layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer.

公开(公告)号：AU3499301A

公开(公告)日：2001-08-20

申请号：AU3499301

申请日：2001-02-08

Applicant: MOTOROLA INC

Inventor： RAMDANI JAMAL ,  DROOPAD RAVINDRANATH ,  HILT LYNDEE L ,  EISENBEISER KURT WILLIAM

IPC: H01L21/331 ,  C30B25/18 ,  H01L21/20 ,  H01L21/205 ,  H01L21/316 ,  H01L21/318 ,  H01L21/822 ,  H01L21/8222 ,  H01L21/8232 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8248 ,  H01L21/8249 ,  H01L21/8252 ,  H01L21/8258 ,  H01L27/04 ,  H01L27/06 ,  H01L27/092 ,  H01L27/095 ,  H01L27/14 ,  H01L27/15 ,  H01L29/26 ,  H01L29/267 ,  H01L29/732 ,  H01L33/16 ,  H01L33/30 ,  H01S5/02 ,  H01S5/026 ,  H01L21/36

Abstract: High quality epitaxial layers of compound semiconductor materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline compound semiconductor layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer.

公开(公告)号：AU3497301A

公开(公告)日：2001-08-20

申请号：AU3497301

申请日：2001-02-08

Applicant: MOTOROLA INC

Inventor： RAMDANI JAMAL ,  DROOPAD RAVINDRANATH ,  HILT LYNDEE L ,  EISENBEISER KURT WILLIAM

IPC: H01L21/331 ,  C30B25/18 ,  H01L21/20 ,  H01L21/205 ,  H01L21/316 ,  H01L21/318 ,  H01L21/822 ,  H01L21/8222 ,  H01L21/8232 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8248 ,  H01L21/8249 ,  H01L21/8252 ,  H01L21/8258 ,  H01L27/04 ,  H01L27/06 ,  H01L27/092 ,  H01L27/095 ,  H01L27/14 ,  H01L27/15 ,  H01L29/26 ,  H01L29/267 ,  H01L29/732 ,  H01L33/16 ,  H01L33/30 ,  H01S5/02 ,  H01S5/026

Abstract: High quality epitaxial layers of compound semiconductor materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline compound semiconductor layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer.

公开(公告)号：DE19708992A1

公开(公告)日：1997-10-30

申请号：DE19708992

申请日：1997-03-05

Applicant: MOTOROLA INC

Inventor： JIANG WENBIN ,  RAMDANI JAMAL ,  LEBBY MICHAEL S

IPC: H01S5/00 ,  H01S5/183 ,  H01S3/085 ,  H01S3/19

Abstract: The VCSEL has a semiconducting substrate (102) with a first divided Bragg reflector (103), with alternating layers (111,112) of InAlGaP and AlAs. These layers are of one dopant type and concentration on one of its surfaces (105). An active region (106) is applied to a covering region (104) and a second covering region (107) is applied to the active region. A second Bragg reflector (108) on the second covering region has alternating layers of InAlGaP and AlAs and of opposite doping type and a different concentration. A contact region (109) is mounted on the second reflector.

公开(公告)号：WO0159821A8

公开(公告)日：2001-11-15

申请号：PCT/US0104388

申请日：2001-02-08

Applicant: MOTOROLA INC

Inventor： RAMDANI JAMAL ,  DROOPAD RAVINDRANATH ,  HILT LYNDEE L ,  EISENBEISER KURT WILLIAM

IPC: H01L21/331 ,  C30B25/18 ,  H01L21/20 ,  H01L21/205 ,  H01L21/316 ,  H01L21/318 ,  H01L21/822 ,  H01L21/8222 ,  H01L21/8232 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8248 ,  H01L21/8249 ,  H01L21/8252 ,  H01L21/8258 ,  H01L27/04 ,  H01L27/06 ,  H01L27/092 ,  H01L27/095 ,  H01L27/14 ,  H01L27/15 ,  H01L29/26 ,  H01L29/267 ,  H01L29/732 ,  H01L33/16 ,  H01L33/30 ,  H01S5/02 ,  H01S5/026 ,  H01L21/36

CPC classification number: H01S5/0261 ,  C30B25/18 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02439 ,  H01L21/02472 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02507 ,  H01L21/02513 ,  H01L21/02521 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02557 ,  H01L21/0256 ,  H01L21/31691 ,  H01L21/8252 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/15 ,  H01L33/16 ,  H01L33/30 ,  H01L2924/0002 ,  H01S5/021 ,  H01L2924/00

Abstract: High quality epitaxial layers of compound semiconductor materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer (24) on a silicon wafer (22). The accommodating buffer layer (24) is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer (28) of silicon oxide. The amorphous interface layer is preferably formed by oxygen diffusion through the oxide buffer and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The process further may comprise formation of template layers (28, 30) and a semiconducteur buffer layer (32). It's especially suited for cointegration of compound semiconducteur and Si SMOS devices.

Abstract translation: 通过首先在硅晶片（22）上生长适应缓冲层（24），可以在大硅晶片上生长高质量的化合物半导体材料外延层。 适应缓冲层（24）是由氧化硅的非晶界面层（28）与硅晶片隔开的单晶氧化物层。 非晶界面层优选通过氧扩散穿过氧化物缓冲层形成，并允许生长高质量的单晶氧化物调节缓冲层。 该过程还可以包括形成模板层（28,30）和半导体缓冲层（32）。 它特别适用于复合半导体和Si SMOS器件的协整。

公开(公告)号：WO0227362A3

公开(公告)日：2003-07-31

申请号：PCT/US0128096

申请日：2001-09-07

Applicant: MOTOROLA INC

Inventor： RAMDANI JAMAL ,  HILT LYNDEE ,  DROOPAD RAVINDRANATH ,  OOMS WILLIAM JAY

IPC: G02B6/12 ,  G02B6/13 ,  G02F1/03 ,  G02F1/035 ,  H01L21/20 ,  G02B6/122 ,  G02B6/132

CPC classification number: G02B6/12004 ,  G02B6/131 ,  G02F1/0338 ,  G02F1/035

Abstract: High quality epitaxial layers of oxide can be grown overlying large silicon wafers (22) by first growing an accommodating buffer layer (26) on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer (24) of silicon oxide. The amorphous intermediate layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous intermediate layer. Waveguides (45) may be formed of high quality monocrystalline material atop the monocrystalline buffer layer. The waveguides can suitably be formed to modulate the wave. Monolithic integration of oxide based electro-optic devices with III-V based photonics and Si circuitry is fully realized.

Abstract translation: 通过首先在硅晶片上生长容纳缓冲层（26），可以生长覆盖大硅晶片（22）的氧化物的高质量外延层。 容纳缓冲层是通过氧化硅的非晶界面层（24）与硅晶片间隔开的单晶氧化物层。 无定形中间层耗散应变并允许高质量单晶氧化物容纳缓冲层的生长。 通过无定形中间层处理容纳缓冲层和下面的硅衬底之间的任何晶格失配。 波导（45）可以由单晶缓冲层顶部的高质量单晶材料形成。 可以适当地形成波导以调制波。 基于氧化物的电光器件与基于III-V的光子学和Si电路的单片集成完全实现。

公开(公告)号：WO03009344A3

公开(公告)日：2003-04-10

申请号：PCT/US0211023

申请日：2002-04-09

Applicant: MOTOROLA INC

Inventor： RAMDANI JAMAL ,  HILT LYNDEE L

IPC: C30B25/18 ,  H01L21/20 ,  H01L33/00 ,  H01L33/12 ,  H01S5/02 ,  H01S5/323

CPC classification number: H01L21/02488 ,  C30B25/18 ,  H01L21/02381 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/0254 ,  H01L21/02546 ,  H01L33/007 ,  H01L33/12 ,  H01S5/021 ,  H01S5/0218 ,  H01S5/32366 ,  H01S2301/173

Abstract: High quality epitaxial layers of monocrystalline III-V arsenide nitride materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. One way to achieve the formation of a compliant substrate includes first growing an accommodating buffer layer (74, 104) on a silicon wafer (72, 102). The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer (78, 108) of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline III-V arsenide nitride material layer. Any lattice mismatch between the accommodating buffer layerand the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, an accommodating buffer layer comprising a barium strontium titanium oxide (104) and a monocrystalline III-V arsenide nitride layer (86, 116), such as GaAsN, having a nitrogen concentration ranging from 1-5% function to further reduce any lattice mismatch between layers.

Abstract translation: 通过形成用于生长单晶层的柔性衬底，可以生长单晶III-V砷化镓材料的高质量外延层，覆盖单晶衬底，例如大硅晶片。 实现柔性衬底的形成的一种方式包括首先在硅晶片（72,102）上生长适应缓冲层（74,104）。 适应缓冲层是由硅氧化物的非晶界面层（78,108）与硅晶片隔开的单晶氧化物层。 非晶界面层消散应变并允许高质量单晶氧化物容纳缓冲层的生长。 适应缓冲层与下面的硅晶片和上面的单晶III-V氮化砷材料层晶格匹配。 适应缓冲层和底层硅衬底之间的任何晶格失配由无定形界面层处理。 另外，包含钡锶钛氧化物（104）和氮浓度范围为1-5％的单晶III-V砷化镓氮化物层（86,116）（例如GaAsN）的调节缓冲层用于进一步减少 层之间的晶格失配。