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公开(公告)号：CA2289212C
公开(公告)日：2008-04-01
申请号：CA2289212
申请日：1998-05-21
Applicant: QUALCOMM INC
Inventor： APARIN VLADIMIR
Abstract: An active phase splitter (100, 102) comprises two or more phase shift circuits (110, 150). Each phase shift circuit comprises a number of active devices (112, 114, 152, 150) and capacitors (116, 156, 158). For a single-pole active phase splitter, within each phase shift circuit, two active devices are configured as a cascode amplifier. The first active device is configured as a common source amplifier and the second active device is configured as a common gate amplifier. A capacitor (116, 156) is connected across the gate and drain of the first active device to generate the necessary pole-zero pair for the phase shift circuit. The cascode configuration results in the desired transfer function and provides transconversion of voltage input (VIA) to current outputs (Ia, Ib). Active phase splitters with two or more poles can be built using the same inventive concept.
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公开(公告)号：RU2305893C2
公开(公告)日：2007-09-10
申请号：RU2003133457
申请日：2002-04-17
Applicant: QUALCOMM INC
Inventor： APARIN VLADIMIR
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公开(公告)号：CA2562908A1
公开(公告)日：2005-10-27
申请号：CA2562908
申请日：2005-03-21
Applicant: QUALCOMM INC
Inventor： WU YUE , APARIN VLADIMIR
Abstract: An integrated circuit Voltage Controlled Oscillator (VCO) in a battery-power ed device, such as a cellular phone, can be configured to tune across a fairly wide frequency range using a relatively narrow control voltage range. The frequency response of the VCO can be temperature compensated by applying a temperature variable voltage source to varactors (310a-310b) that form part of a VCO resonant circuit. The reference ends of the varactors can be supplied with a temperature dependent voltage source (370, 380) that has a temperatur e dependence that substantially compensates for varactor temperature dependenc e. The temperature dependent voltage source (370, 380) can be a Proportional To Absolute Temperature (PTAT) device. The VCO includes a CMOS oscillator manufactured on the substrate, an LC resonant tank on the substrate and at least a pair of varacters (310a, 310b; 320a, 320b) having a common anode connection.
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公开(公告)号：ES2228464T3
公开(公告)日：2005-04-16
申请号：ES00905612
申请日：2000-01-13
Applicant: QUALCOMM INC
Inventor： APARIN VLADIMIR
Abstract: Circuito para convertir una señal de corriente diferencial en una señal asimétrica, que comprende: un dispositivo activo (200) que presenta un terminal de control, un terminal generador de carga y un terminal colector de carga y una resistencia (210) que presenta dos terminales; en el que se aplica un potencial de polarización por lo menos indirectamente al terminal generador de carga de dicho dispositivo activo, en el que uno de los dos terminales de dicha resistencia está conectado al terminal colector de carga de dicho dispositivo activo (200), y el otro de los dos terminales de dicha resistencia (210) está conectado al terminal de control de dicho dispositivo activo y en el que la señal de corriente diferencial se aplica a los terminales de la resistencia (210), y la señal asimétrica se pasa al terminal colector de carga de dicho dispositivo activo (200).
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公开(公告)号：AT277457T
公开(公告)日：2004-10-15
申请号：AT00905612
申请日：2000-01-13
Applicant: QUALCOMM INC
Inventor： APARIN VLADIMIR
Abstract: Many applications require the conversion of a differential current signal into a single-ended signal. The shortcomings encountered with existing approaches include poor conversion efficiency, limited bandwidth, and large size. The converter disclosed uses active devices to obtain a unit of small size and high efficiency having a wide bandwidth of operation.
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Patent Agency Ranking
公开(公告)号：MXPA03002989A
公开(公告)日：2004-05-05
申请号：MXPA03002989
申请日：2001-10-06
Applicant: QUALCOMM INC
Inventor： APARIN VLADIMIR
IPC: H02H9/04
Abstract: Una disposicion para proteger un elemento de una descarga electrostatica; se provee un interruptor para inhibir el flujo de energia a traves del elemento en respuesta a la senal de control; en la modalidad ilustrativa, el interruptor es un interruptor de transistor; se coloca un resistor entre una terminal de entrada del transistor y el suministro positivo para mantener el transistor activo durante la operacion normal; se coloca un capacitor entre la terminal de entrada del transistor y la toma de tierra para evitar que el voltaje de entrada del transistor cambie rapido; la constante de tiempo RC se elige para que sea mucho mayor que la constante de tiempo del pulso ESD; por consecuencia, el voltaje de entrada del transistor permanecera sin modificacion alguna cerca de V y el transistor permanecera inactivo durante el evento ESD, evitando que el elemento dirija la corriente de descarga y proporcionando proteccion ESD.
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公开(公告)号：RU2216874C2
公开(公告)日：2003-11-20
申请号：RU2000120619
申请日：1999-01-06
Applicant: QUALCOMM INC
Inventor： KAUFMAN RAL F E , APARIN VLADIMIR
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公开(公告)号：AU764395B2
公开(公告)日：2003-08-14
申请号：AU2164500
申请日：1999-12-03
Applicant: QUALCOMM INC
Inventor： APARIN VLADIMIR , PERSICO CHARLES K
Abstract: Techniques to reduce intermodulation distortion at the output of an active circuit having even-order and odd-order nonlinearities. The IM3 products generated by the even-order nonlinearity of the active circuit are canceled against the IM3 products generated by the odd-order nonlinearity. The amplitude and phase of the IM3 products can be manipulated by adjusting either the source or load impedance, or both, of the active circuit. The amplitude and phase of the IM2 products generated by the even-order nonlinearity can be manipulated by adjusting the impedance of the active circuit at sub-harmonic and second harmonic frequencies (i.e., the frequencies of the IM2 products). The amplitude and phase of the IM3 products generated by the odd-order nonlinearity can be manipulated by adjusting the impedance of the active circuit at the fundamental frequency. By properly tuning or "matching" the impedance of either the source or load, or both, of the active circuit at either the sub-harmonic or second harmonic frequency, or both, the amplitude and phase of the IM2 products can be adjusted such that the IM3 products resulting from the even-order nonlinearity approximately cancel the IM3 product(s) resulting from the odd-order nonlinearity.
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公开(公告)号：AU760605B2
公开(公告)日：2003-05-15
申请号：AU2028299
申请日：1999-01-06
Applicant: QUALCOMM INC
Inventor： KAUFMAN RALPH E , APARIN VLADIMIR
Abstract: A quadrature modulator and demodulator which provide the requisite level of performance while minimizing power consumption. In the quadrature modulator, the I and Q signals are provided to two pairs of mixers. Each mixer in a pair of mixers modulates an I or Q signal with the respective inphase or quadrature IF sinusoid. The I and Q modulated signals from each pair of mixers are summed. The signals from the summers are provided to a third pair of mixer and modulated with the respective inphase and quadrature RF sinusoids. The signals from the third pair of mixers are summed and provided as the modulated signal. Using this quadrature modulator topology, the amplitude balance and phase error of the modulated signal are made insensitive to the amplitude imbalance and/or phase error of the quadrature splitters used to generate the IF and RF sinusoids. Furthermore, since the first two pairs of mixers and the two subsequent summers are operated at IF frequency, the performance requirements (e.g., bandwidth and linearity) of these components can be ensured while utilizing less power. The inventive concept can be further adopted for use in a quadrature demodulator.
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公开(公告)号：CA2427913A1
公开(公告)日：2002-07-18
申请号：CA2427913
申请日：2001-10-31
Applicant: QUALCOMM INC
Inventor： APARIN VLADIMIR , SHAH PETER J
Abstract: A radio frequency amplifier with improved linearity and minimal third-order distortion. The amplifier includes a first transistor having first, second and third terminals with the first terminal being an input terminal and the second terminal being the output terminal and the third terminal being a common terminal. A linearization circuit is included having first and second terminals. The first terminal is connected to the common terminal of the transistor and the second terminal is connected to the input terminal of the transistor. In a specific embodiment, the linearization circuit is implemented as a unity gain buffer with an input terminal connected to the common terminal of the transistor and an output terminal connected to the input terminal of the transistor. In accordance with the inventive teachings, the buffer has a low gain and high output impedance at first frequency (f1) of a first signal applied to the circuit and a second frequency (f2) of a second signal applied to the circuit and a unity gain and low output impedance a difference between the first and second frequencies. In another specific embodiment, the inductor is inserted between the output of the unity gain buffer and the input terminal of the transistor. In alternative embodiments, circuitry is shown for providing adirect current offset at the input of the transistor. As another alternative, the linearization circuit consists of series inductor and capacitor connected between the common and input terminals of the transistor. In yet another embodiment, the linearization circuit consists of the first and the second series inductor and capacitor circuits. The first series LC circuit is connected between the common terminal of the transistor and ground and the second series LC circuit is connected between the input terminal of the transistor and ground.
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