公开(公告)号：WO2008112318A3

公开(公告)日：2008-11-13

申请号：PCT/US2008003473

申请日：2008-03-13

Applicant: TESSERA INC ,  HABA BELGACEM ,  KUBOTA YOICHI ,  KANG TECK-GYU ,  PARK JAE M

Inventor： HABA BELGACEM ,  KUBOTA YOICHI ,  KANG TECK-GYU ,  PARK JAE M

IPC: H05K1/11 ,  H01L23/48

CPC classification number: H01L24/14 ,  H01L21/4828 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/49811 ,  H01L24/11 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/73203 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01084 ,  H01L2924/01322 ,  H01L2924/014 ,  H05K3/061 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2203/0369 ,  H05K2203/0597 ,  H05K2203/1476 ,  Y10T29/49126 ,  Y10T428/24174 ,  H01L2224/05599

Abstract: A method includes applying a final etch-resistant material 34 to an in-process substrate 10 so that the final etch-resistant material 34 at least partially covers first microcontact portions 32 integral with the substrate 10 and projecting upwardly from a surface 18 of the substrate, and etching the surface of the substrate 10 so as to leave second microcontact portions 36 below the first microcontact portions 32 and integral therewith, the final etch-resistant material 34 at least partially protecting the first microcontact portions 32 from etching during the further etching step. A microelectronic unit includes a substrate 10, and a plurality of microcontacts 38 projecting in a vertical direction from the substrate 10, each microcontact 38 including a base region 42 adjacent the substrate and a tip region 32 remote from the substrate, each microcontact 38 having a horizontal dimension which is a first function of vertical location in the base region 42 and which is a second function of vertical location in the tip region 32.

Abstract translation: 一种方法包括将最终的耐蚀刻材料34施加到工艺衬底10，使得最终抗蚀刻材料34至少部分地覆盖与衬底10成一体并从衬底的表面18向上突出的第一微接触部分32 并且蚀刻衬底10的表面以便将第二微接触部分36留在第一微接触部分32下方并与之成一体，最终抗蚀刻材料34在另外的蚀刻步骤期间至少部分地保护第一微接触部分32免受蚀刻 。 微电子单元包括衬底10和从衬底10沿垂直方向突出的多个微接点38，每个微接触器38包括邻近衬底的基极区域42和远离衬底的尖端区域32，每个微接触器38具有 水平尺寸是基部区域42中的垂直位置的第一函数，并且其是尖端区域32中的垂直位置的第二函数。

公开(公告)号：WO2008045422A3

公开(公告)日：2008-10-02

申请号：PCT/US2007021552

申请日：2007-10-09

Applicant: TESSERA INC ,  HABA BELGACEM ,  OGANESIAN VAGE

Inventor： HABA BELGACEM ,  OGANESIAN VAGE

IPC: H01L25/065 ,  H01L21/98 ,  H01L23/538

CPC classification number: H01L25/0657 ,  H01L21/78 ,  H01L23/5382 ,  H01L24/48 ,  H01L25/50 ,  H01L2224/24145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06568 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

Abstract: In accordance with an aspect of the invention, a stacked microelectronic package (280) is provided which may include a plurality of subassemblies (210), e.g., a first subassembly and a second subassembly underlying the first subassembly. A front face of the second subassembly may confront the rear face of the first subassembly. Each of the first and second subassemblies may include a plurality of front contacts (2668) exposed at the front face, at least one edge and a plurality of front traces (2666) extending about the respective at least one edge. The second subassembly may have a plurality of rear contacts (2968) exposed at the rear face. The second subassembly may also have a plurality of rear traces (2966) extending from the rear contacts about the at least one edge. The rear traces may extend to at least some of the plurality of front contacts of at least one of the first or second subassemblies.

Abstract translation: 根据本发明的一个方面，提供了堆叠的微电子封装（280），其可以包括多个子组件（210），例如第一子组件和位于第一子组件下方的第二子组件。 第二子组件的前表面可面对第一子组件的后表面。 第一和第二子组件中的每一个可以包括在前表面处暴露的多个前触点（2668），至少一个边缘和围绕相应的至少一个边缘延伸的多个前迹线（2666）。 第二子组件可以具有在后表面处暴露的多个后触点（2968）。 第二子组件还可以具有从后接触件围绕至少一个边缘延伸的多个后迹线（2966）。 后迹线可以延伸到第一或第二子组件中的至少一个的多个前触点中的至少一些。

公开(公告)号：WO2008108970A2

公开(公告)日：2008-09-12

申请号：PCT/US2008002659

申请日：2008-02-26

Applicant: TESSERA INC ,  HABA BELGACEM ,  HONER KENNETH ALLEN ,  TUCKERMAN DAVID B ,  OGANESIAN VAGE

Inventor： HABA BELGACEM ,  HONER KENNETH ALLEN ,  TUCKERMAN DAVID B ,  OGANESIAN VAGE

IPC: H01L23/31 ,  H01L23/48 ,  H01L23/485 ,  H01L25/065 ,  H01L27/146 ,  H01L29/06 ,  H01L31/0203

CPC classification number: H01L23/3128 ,  H01L23/481 ,  H01L24/10 ,  H01L24/13 ,  H01L27/14618 ,  H01L27/14683 ,  H01L29/0657 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05026 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/07811 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3025 ,  H04N5/2257 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A microelectronic unit is provided in which front (102) and rear (114) surfaces of a semiconductor element (100) may define a thin region (105) which has a first thickness and a thicker region having a thickness at least about twice the first thickness. A semiconductor device (112) may be present at the front surface, with a plurality of first conductive contacts (116) at the front surface connected to the device. A plurality of conductive vias (125) may extend from the rear surface through the thin region (105) of the semiconductor element to the first conductive contacts (116). A plurality of second conductive contacts (134) can be exposed at an exterior of the semiconductor element (100). A plurality of conductive traces (126) may connect the second conductive contacts (134) to the conductive vias (125).

Abstract translation: 提供了一种微电子单元，其中半导体元件（100）的前部（102）和后部（114）表面可以限定一个薄区域（105），该薄区域具有第一厚度和较厚的区域，其厚度至少为第一厚度的两倍 厚度。 可以在前表面处存在半导体器件（112），在连接到器件的前表面处具有多个第一导电触点（116）。 多个导电通孔（125）可以从后表面延伸穿过半导体元件的薄区（105）到第一导电触点（116）。 多个第二导电触点（134）可以在半导体元件（100）的外部暴露。 多个导电迹线（126）可以将第二导电触点（134）连接到导电通孔（125）。

公开(公告)号：WO2008036208A3

公开(公告)日：2008-07-24

申请号：PCT/US2007020038

申请日：2007-09-14

Applicant: TESSERA INC ,  KANG TECK-GYU ,  HABA BELGACEM ,  GAO GUILIAN

Inventor： KANG TECK-GYU ,  HABA BELGACEM ,  GAO GUILIAN

IPC: H01L21/60 ,  H01L23/485

CPC classification number: H01L24/16 ,  H01L21/4853 ,  H01L23/3114 ,  H01L23/49811 ,  H01L24/02 ,  H01L24/11 ,  H01L24/12 ,  H01L24/81 ,  H01L2224/02125 ,  H01L2224/0231 ,  H01L2224/0236 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/11334 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2224/29099

Abstract: Wafer level chip packages including risers (230) having sloped sidewalls (206) with conductive lines (240) on the sloped sidewalls and methods of fabricating such chip packages are disclosed. The inventive wafer level chip packages may advantageously be used in various microelectronic assemblies.

Abstract translation: 公开了一种晶片级芯片封装，其包括在倾斜侧壁上具有导线（240）的具有倾斜侧壁（206）的立管（230）和制造这种芯片封装的方法。 本发明的晶片级芯片封装可有利地用于各种微电子组件中。

公开(公告)号：WO2008048666A3

公开(公告)日：2008-07-10

申请号：PCT/US2007022233

申请日：2007-10-17

Applicant: TESSERA INC ,  HUMPSTON GILES ,  GAO GUILIAN ,  HABA BELGACEM

Inventor： HUMPSTON GILES ,  GAO GUILIAN ,  HABA BELGACEM

IPC: H01L23/498

CPC classification number: H01L23/4985 ,  H01L23/49811 ,  H01L24/48 ,  H01L2224/45014 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/3011 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A microelectronic package 700 includes a microelectronic element 702 having contacts 706, a flexible substrate 712 spaced from and overlying the microelectronic element and a plurality of conductive posts 726 extending from the flexible substrate 712 and projecting away from the microelectronic element 702. The conductive posts are electrically interconnected with the microelectronic element. Each conductive post has a conductive base 728 that is in contact with the flexible substrate 712 and a conductive tip 730 that extends from the base, with the base of the conductive post having a larger diameter than the tip of the conductive post. In certain embodiments, the conductive base and the conductive tip have a cylindrical shape.

Abstract translation: 微电子封装700包括微电子元件702，微电子元件702具有触点706，与微电子元件间隔开并且覆盖微电子元件的柔性衬底712以及从柔性衬底712延伸并远离微电子元件702突出的多个导电柱726。 与微电子元件电互连。 每个导电柱具有与柔性衬底712接触的导电基部728和从基部延伸的导电尖端730，其中导电柱的基部的直径大于导电柱的尖端的直径。 在某些实施例中，导电基底和导电尖端具有圆柱形状。

公开(公告)号：WO2007075678A3

公开(公告)日：2007-10-25

申请号：PCT/US2006048423

申请日：2006-12-19

Applicant: TESSERA INC ,  HABA BELGACEM ,  MITCHELL CRAIG S

Inventor： HABA BELGACEM ,  MITCHELL CRAIG S

IPC: H01L23/498 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L25/50 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/3011 ,  H01L2924/3511

Abstract: A method of making a stacked microelectronic assembly includes providing a first microelectronic package 122A having a first substrate 124A and conductive posts 130A extending from a surface 128A of the first substrate 124A, and providing a second microelectronic package 122B having a second substrate 124B and conductive, fusible masses 148B extending from a surface 126B of the second substrate 124B. A microelectronic element 154A is secured over one of the surfaces of the first and second substrates 124A, 124B, the microelectronic element 154A defining a vertical height H 1 that extends from the one of the surfaces of the first and second substrate to which the microelectronic element is secured. The tips 131A of the conductive posts 130A of the first substrate are abutted against the apexes of the fusible masses 148B of the second substrate, whereby the vertical height of each conductive post/fusible mass combination is equal to or greater than the vertical height of the microelectronic element 154A secured to the one of the surfaces of said first and second substrates.

Abstract translation: 制造堆叠的微电子组件的方法包括提供具有第一衬底124A的第一微电子封装122A和从第一衬底124A的表面128A延伸的导电柱130A，以及提供具有第二衬底124B的第二微电子封装122B， 可熔体148B从第二基板124B的表面126B延伸。 微电子元件154A固定在第一和第二基板124A，124B的一个表面上，微电子元件154A限定从第一和第二基板124A，124B的表面之一延伸的垂直高度H 1 微电子元件固定到其上的第二基板。 第一基板的导电柱130A的尖端131A抵靠第二基板的可熔块148B的顶点，由此​​每个导电柱/可熔组合的垂直高度等于或大于 微电子元件154A固定在所述第一和第二基板的一个表面上。

公开(公告)号：WO2007076099A2

公开(公告)日：2007-07-05

申请号：PCT/US2006049202

申请日：2006-12-26

Applicant: TESSERA INC ,  HABA BELGACEM ,  MOHAMMED ILYAS ,  MITCHELL CRAIG S ,  WARNER MICHAEL ,  THOMPSON JESSE BURL

Inventor： HABA BELGACEM ,  MOHAMMED ILYAS ,  MITCHELL CRAIG S ,  WARNER MICHAEL ,  THOMPSON JESSE BURL

CPC classification number: H01L21/6835 ,  H01L22/34 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05024 ,  H01L2224/05026 ,  H01L2224/05548 ,  H01L2224/056 ,  H01L2224/11003 ,  H01L2224/1134 ,  H01L2224/131 ,  H01L2224/13582 ,  H01L2224/136 ,  H01L2224/1601 ,  H01L2224/81193 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05099

Abstract: A dielectric structure is formed by a molding process, so that a first surface (32, 432) of a dielectric structure is shaped by contact with the mold. The opposite second surface (34, 434) of the dielectric structure is applied onto the front surface of a wafer element (38, 438). The dielectric structure may include protruding bumps (30, 130, 230) and terminals (44, 144, 244) may be formed on the bumps. The bumps may be of a precise height. The terminals lie at a precisely controlled height above the front surface of the wafer element. The terminals may include projecting posts (213, 413) which extend above a surrounding solder mask layer (248, 448) to facilitate engagement with a test fixture. The posts are immersed within solder joints (274) when the structure is bonded to a circuit panel.

Abstract translation: 介电结构通过模制工艺形成，使得介电结构的第一表面（32,432）通过与模具接触而成形。 介电结构的相对的第二表面（34,434）被施加到晶片元件（38,438）的前表面上。 电介质结构可以包括突起凸块（30,130,230），并且端子（44,144,244）可以形成在凸块上。 颠簸可能具有精确的高度。 端子位于晶片元件的前表面上方的精确控制高度处。 端子可以包括在周围的阻焊层（248,448）之上延伸的突出柱（213,413），以便于与测试夹具接合。 当结构粘合到电路板时，柱被浸入焊点（274）内。

公开(公告)号：WO2006012127A2

公开(公告)日：2006-02-02

申请号：PCT/US2005021968

申请日：2005-06-21

Applicant: TESSERA INC ,  HABA BELGACEM ,  BEROZ MASUD ,  KANG TECK-GYU ,  KUBOTA YOICHI ,  KRISHNAN SRIDHAR ,  RILEY JOHN B III ,  MOHAMMED ILYAS

Inventor： HABA BELGACEM ,  BEROZ MASUD ,  KANG TECK-GYU ,  KUBOTA YOICHI ,  KRISHNAN SRIDHAR ,  RILEY JOHN B III ,  MOHAMMED ILYAS

IPC: H01L23/02 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L25/10

CPC classification number: H01L23/49811 ,  H01L23/3128 ,  H01L23/3677 ,  H01L23/4985 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A microelectronic package (90) includes a microelectronic element (62) having faces, contacts and an outer perimeter, and a flexible substrate (42) overlying and spaced from a first face of the Microelectronic element (62), an outer region (86) of the flexible substrate (42) extending beyond the outer perimeter of the Microelectronic element (62). The package (90) includes a plurality of conductive posts (40a-40f) exposed at a surface of the flexible substrate (42) and being electrically interconnected with the microelectronic element (62), whereby at least one of the conductive posts (40a-40f) is disposed in the outer region (86) of the flexible substrate (42), and a compliant layer (74) disposed between the first face of the microelectronic element (62) and the flexible substrate (42), wherein the compliant layer (74) overlies the at least one of the conductive posts that is disposed in the outer region (86) of the flexible substrate (42). The package includes a support element (84) in contact with the microelectronic element (62) and the compliant layer (74), whereby the support element 84 overlies the outer region (86) of the flexible substrate (42).

Abstract translation: 微电子封装（90）包括具有面，触点和外周边的微电子元件（62），以及覆盖并与微电子元件（62）的第一面间隔开的柔性基板（42），外部区域（86） 所述柔性基底（42）延伸超出所述微电子元件（62）的外周边。 封装（90）包括在柔性基板（42）的表面处暴露并与微电子元件（62）电互连的多个导电柱（40a-40f），由此至少一个导电柱（40a- 40f）设置在柔性基板（42）的外部区域（86）中，以及设置在微电子元件（62）的第一面和柔性基板（42）之间的顺应层（74），其中柔顺层 （74）覆盖设置在柔性基板（42）的外部区域（86）中的至少一个导电柱。 该封装包括与微电子元件（62）和柔性层（74）接触的支撑元件（84），由此支撑元件84覆盖柔性基板（42）的外部区域（86）。

公开(公告)号：WO2004077525A2

公开(公告)日：2004-09-10

申请号：PCT/US2004005629

申请日：2004-02-25

Applicant: TESSERA INC

Inventor： HABA BELGACEM ,  KUBOTA YOICHI

IPC: H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L25/10 ,  H01L

CPC classification number: H01L23/3114 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/4985 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/05599 ,  H01L2224/16 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor chip assembly includes a chip carrier having a dielectric layer (22) and electrically-conductive terminals in the form of projecting bumps (52) formed integrally with traces (38) an the dielectric layer. The bumps (52) have convex surfaces and desirably are hollow and deformable. The convex bottom ends of the bumps may be bonded to the contact pads (92) an the surfaces of a circuit panel by a small amount of solder or other bonding material (100). The structure provides a sound joint between the contact pads and the bumps and avoids the need for relatively large solder balls. The assembly can be made using techniques well-integrated with conventional surface-mounting techniques.

Abstract translation: 半导体芯片组件包括具有电介质层（22）的芯片载体和与电介质层的迹线（38）整体形成的突出凸块（52）形式的导电端子。 凸起（52）具有凸形表面，并且期望地是中空的和可变形的。 凸起的凸起的底端可以通过少量的焊料或其它粘结材料（100）与电路板的表面接合到接触焊盘（92）。 该结构在接触垫和凸起之间提供声音接合，并避免了对较大焊锡球的需要。 可以使用与常规表面贴装技术良好集成的技术制造组件。