公开(公告)号：US20230380295A1

公开(公告)日：2023-11-23

申请号：US18229661

申请日：2023-08-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Ya-Sheng Feng

IPC: H10N50/80 ,  H01L21/768 ,  H10N50/01

CPC classification number: H10N50/80 ,  H01L21/76838 ,  H01L21/76801 ,  H10N50/01

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a metal interconnection in the first IMD layer; forming a bottom electrode layer and a pinned layer on the first IMD layer; forming a sacrificial layer on the pinned layer; patterning the sacrificial layer, the pinned layer, and the bottom electrode layer to form a first magnetic tunneling junction (MTJ); forming a second IMD layer around the first MTJ; and removing the sacrificial layer.

公开(公告)号：US11765982B2

公开(公告)日：2023-09-19

申请号：US17900898

申请日：2022-09-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Ya-Sheng Feng

IPC: H10N50/80 ,  H01L21/768 ,  H10N50/01

CPC classification number: H10N50/80 ,  H01L21/76801 ,  H01L21/76838 ,  H10N50/01

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a metal interconnection in the first IMD layer; forming a bottom electrode layer and a pinned layer on the first IMD layer; forming a sacrificial layer on the pinned layer; patterning the sacrificial layer, the pinned layer, and the bottom electrode layer to form a first magnetic tunneling junction (MTJ); forming a second IMD layer around the first MTJ; and removing the sacrificial layer.

公开(公告)号：US20220416153A1

公开(公告)日：2022-12-29

申请号：US17900898

申请日：2022-09-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Ya-Sheng Feng

IPC: H01L43/02 ,  H01L21/768 ,  H01L43/12

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a metal interconnection in the first IMD layer; forming a bottom electrode layer and a pinned layer on the first IMD layer; forming a sacrificial layer on the pinned layer; patterning the sacrificial layer, the pinned layer, and the bottom electrode layer to form a first magnetic tunneling junction (MTJ); forming a second IMD layer around the first MTJ; and removing the sacrificial layer.

公开(公告)号：US20200098584A1

公开(公告)日：2020-03-26

申请号：US16692435

申请日：2019-11-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung

IPC: H01L21/3105 ,  H01L23/522 ,  H01L23/00 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/06

Abstract: A manufacturing method of a semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate having an active component region and a non-active component region, a first dielectric layer, a second dielectric layer, high resistivity metal segments, dummy stacked structures and a metal connection structure. The high resistivity metal segments are formed in the second dielectric layer and located in the non-active component region. The dummy stacked structures are located in the non-active component region, and at least one dummy stacked structure penetrates through the first dielectric layer and the second dielectric layer and is located between two adjacent high resistivity metal segments. The metal connection structure is disposed on the second dielectric layer, and the high resistivity metal segments are electrically connected to one another through the metal connection structure.

公开(公告)号：US10600882B2

公开(公告)日：2020-03-24

申请号：US14880275

申请日：2015-10-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Yi-Wei Chen ,  Chun-Hsien Lin

IPC: H01L21/70 ,  H01L29/49 ,  H01L29/423

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a substrate, and an interlayer dielectric disposed on the substrate which has agate structure therein. The gate structure further includes a gate electrode with a protruding portion, and a gate dielectric layer disposed between the gate electrode and the substrate. A spacer is disposed between the interlayer dielectric and the gate electrode. An insulating cap layer is disposed atop the gate electrode and encompasses the top and the sidewall of the protruding portion.

公开(公告)号：US10535817B1

公开(公告)日：2020-01-14

申请号：US16144888

申请日：2018-09-27

Applicant: United Microelectronics Corp.

Inventor： Ching-Wen Hung ,  Kun-Ju Li

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02 ,  H01L43/10 ,  H01L43/08

Abstract: A method of manufacturing an embedded magnetoresistive random access memory including the following steps is provided. A memory cell stack structure is formed on a substrate structure. The memory cell stack structure includes a first electrode, a second electrode, and a magnetic tunnel junction structure. A first dielectric layer covering the memory cell stack structure is formed. A metal nitride layer is formed on the first dielectric layer. A second dielectric layer is formed on the metal nitride layer. A first CMP process is performed on the second dielectric layer to expose the metal nitride layer by using the metal nitride layer as a stop layer. An etch back process is performed to completely remove the metal nitride layer and expose the first dielectric layer. A second CMP process is performed to expose the second electrode. The manufacturing method can have a better planarization effect.

公开(公告)号：US10529580B2

公开(公告)日：2020-01-07

申请号：US15698765

申请日：2017-09-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung

IPC: H01L21/3105 ,  H01L27/088 ,  H01L21/8234 ,  H01L23/00 ,  H01L23/522

Abstract: A semiconductor device structure and a manufacturing method thereof are provided. The semiconductor device structure includes a semiconductor substrate having an active component region and a non-active component region, a first dielectric layer, a second dielectric layer, high resistivity metal segments, dummy stacked structures and a metal connection structure. The high resistivity metal segments are formed in the second dielectric layer and located in the non-active component region. The dummy stacked structures are located in the non-active component region, and at least one dummy stacked structure penetrates through the first dielectric layer and the second dielectric layer and is located between two adjacent high resistivity metal segments. The metal connection structure is disposed on the second dielectric layer, and the high resistivity metal segments are electrically connected to one another through the metal connection structure.

公开(公告)号：US20190252544A1

公开(公告)日：2019-08-15

申请号：US16392591

申请日：2019-04-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung

IPC: H01L29/78 ,  H01L21/8238 ,  H01L29/417 ,  H01L29/10 ,  H01L29/423 ,  H01L29/786 ,  H01L27/092

CPC classification number: H01L29/7813 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/1037 ,  H01L29/1606 ,  H01L29/41733 ,  H01L29/41766 ,  H01L29/4238 ,  H01L29/42384 ,  H01L29/78642 ,  H01L29/78681

Abstract: A semiconductor device includes a first dielectric layer on a substrate, a hard mask layer on the first dielectric layer, a trench in the hard mask layer and the first dielectric layer, a first source/drain electrode layer on a sidewall of the trench, a second dielectric layer on the first source/drain electrode layer in the trench, a second source/drain electrode layer on the second dielectric layer in the trench, a third dielectric layer on the second source/drain electrode layer in the trench, a 2D material layer overlying the hard mask layer, the first source/drain electrode layer, the second dielectric layer, the second source/drain electrode layer, and the third dielectric layer, a gate dielectric layer on the 2D material layer, and a gate electrode on the gate dielectric layer.

公开(公告)号：US10199374B2

公开(公告)日：2019-02-05

申请号：US15825057

申请日：2017-11-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Hsiang-Hung Peng ,  Wei-Hao Huang ,  Ching-Wen Hung ,  Chih-Sen Huang

IPC: H01L27/06 ,  H01L21/768 ,  H01L21/8234 ,  H01L49/02

Abstract: A method for fabricating semiconductor device is disclosed. A substrate having a first transistor on a first region, a second transistor on a second region, a trench isolation region, a resistor-forming region is provided. A first ILD layer covers the first region, the second region, and the resistor-forming region. A resistor material layer and a capping layer are formed over the first region, the second region, and the resistor-forming region. The capping layer and the resistor material layer are patterned to form a first hard mask pattern above the first and second regions and a second hard mask pattern above the resistor-forming region. The resistor material layer is isotropically etched. A second ILD layer is formed over the substrate. The second ILD layer and the first ILD layer are patterned with a mask and the first hard mask pattern to form a contact opening.

公开(公告)号：US10170376B1

公开(公告)日：2019-01-01

申请号：US15790048

申请日：2017-10-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung

IPC: H01L31/062 ,  H01L31/113 ,  H01L21/8238 ,  H01L21/768 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L23/535 ,  H01L21/02 ,  H01L21/225 ,  H01L21/324 ,  H01L21/285 ,  H01L27/092

Abstract: A device includes a first vertical nanowire, a second vertical nanowire and a gate. The first vertical nanowire is disposed on a substrate, wherein the first vertical nanowire includes a silicon germanium channel part. The second vertical nanowire is disposed on the substrate beside the first vertical nanowire, wherein the second vertical nanowire includes a silicon channel part. The gate encircles the silicon germanium channel part and the silicon channel part. The present invention provides a method of forming said device including the following steps. A substrate is provided. A silicon vertical nanowire is formed on the substrate. A germanium containing layer is formed on sidewalls of the silicon vertical nanowire. Germanium atoms of the germanium containing layer are driven into the silicon vertical nanowire, thereby forming a silicon germanium channel part of the silicon vertical nanowire. A gate encircling the silicon germanium channel part is formed.