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61.发明申请公开(公告)号：US20180359854A1
公开(公告)日：2018-12-13
申请号：US16106938
申请日：2018-08-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Doh Won JUNG , Se Yun KIM , Jong Wook ROH , Jongmin LEE , Sungwoo HWANG , Jinyoung HWANG , Chan KWAK
IPC: H05K1/09 , C09D7/40 , C09D1/00 , C01G55/00 , C09D5/24 , H05K3/28 , H05K1/02 , C08K3/22 , B82Y40/00 , B82Y30/00
CPC classification number: H05K1/09 , B82Y30/00 , B82Y40/00 , C01G55/004 , C01P2002/72 , C01P2002/85 , C01P2004/03 , C01P2004/04 , C01P2004/24 , C01P2004/61 , C01P2006/40 , C08K3/22 , C09D1/00 , C09D5/24 , C09D7/70 , H05K1/0274 , H05K3/28 , H05K2201/026 , H05K2201/0302 , H05K2201/032 , H05K2201/0326 , H05K2201/0338 , H05K2201/0776 , H05K2201/10977 , Y10S977/755 , Y10S977/896 , Y10S977/932
Abstract: An electrical conductor includes a substrate; and a first conductive layer disposed on the substrate and including a plurality of metal oxide nanosheets, wherein adjacent metal oxide nanosheets of the plurality of metal oxide nanosheets contact to provide an electrically conductive path between the contacting metal oxide nanosheets, wherein the plurality of metal oxide nanosheets include an oxide of Re, V, Os, Ru, Ta, Ir, Nb, W, Ga, Mo, In, Cr, Rh, Mn, Co, Fe, or a combination thereof, and wherein the metal oxide nanosheets of the plurality of metal oxide nanosheets have an average lateral dimension of greater than or equal to about 1.1 micrometers. Also an electronic device including the electrical conductor, and a method of preparing the electrical conductor.
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公开(公告)号：US20180302056A1
公开(公告)日：2018-10-18
申请号：US15591212
申请日：2017-05-10
Applicant: AMBIT MICROSYSTEMS (SHANGHAI) LTD.
Inventor： MING-HSIEN HSU , SHII-RONG DEN
CPC classification number: H03H7/03 , H05K1/0242 , H05K1/115 , H05K2201/0373 , H05K2201/0776
Abstract: A filter is disposed on a base board. The filter includes a first portion, a second portion, a ground portion, a first coupling portion and a second coupling portion. The first portion is disposed on a first layer in the base board to input signals. The second portion is disposed on the first layer to output signals. The ground portion is disposed on a second layer in the base board. The first coupling portion is disposed on the first layer. The first coupling portion is electrically coupled to the first portion and the second portion. The first coupling portion is electrically coupled to the ground portion through via holes. The second coupling portion is disposed on the first layer. The second coupling portion is electrically coupled to the first portion and the second portion. The second coupling portion is electrically coupled to the ground portion through the via holes.
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公开(公告)号：US09992871B2
公开(公告)日：2018-06-05
申请号：US14937047
申请日：2015-11-10
Applicant: Intel Corporation
Inventor： William J. Lambert , Mathew J Manusharow
CPC classification number: H05K1/116 , H05K1/0234 , H05K1/115 , H05K1/181 , H05K3/0047 , H05K3/32 , H05K3/4069 , H05K3/4084 , H05K3/4644 , H05K2201/0329 , H05K2201/0391 , H05K2201/0776 , H05K2201/09627 , H05K2201/10015 , H05K2203/14
Abstract: Discussed generally herein are methods and devices for altering an effective series resistance (ESR) of a component. A device can include a substrate including electrical connection circuitry therein, a first via hole through a first surface of the substrate and contiguous with the electrical connection circuitry, a first conductive polymer with a resistance greater than a resistance of the electrical connection circuitry filling the first via hole, and a component electrically coupled to the first conductive polymer.
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64.发明授权公开(公告)号：US09788418B2
公开(公告)日：2017-10-10
申请号：US14902980
申请日：2014-07-07
Applicant: INKTEC Co., Ltd.
Inventor： Kwang-Choon Chung , Ji Hoon Yoo , Joonki Seong , Byung Hun Kim , Nam-Boo Cho , Myung-Bong Yoo
IPC: H01K1/02 , H05K3/00 , H05K1/09 , H05K3/12 , H05K3/06 , H05K1/03 , H05K1/02 , G06F3/041 , H01L51/44
CPC classification number: H05K1/0274 , G06F3/041 , G06F2203/04103 , H01L51/445 , H05K1/0213 , H05K1/0289 , H05K1/0298 , H05K1/0306 , H05K1/032 , H05K1/034 , H05K1/0346 , H05K1/097 , H05K3/0026 , H05K3/06 , H05K3/067 , H05K3/12 , H05K3/1258 , H05K2201/0776 , Y02E10/549 , Y02P70/521
Abstract: Provided herein is a method for manufacturing a conductive transparent substrate, the method including forming a plurality of main electrodes on the substrate such that the main electrodes are distanced from one another; and forming a connecting electrode that electrically connects two or more main electrodes such that the plurality of main electrodes are grouped into a plurality of group electrodes that are electrically disconnected from one another, thereby producing a conductive transparent substrate with excellent transmittance in a process of high yield.
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公开(公告)号：US20170135211A1
公开(公告)日：2017-05-11
申请号：US14937047
申请日：2015-11-10
Applicant: Intel Corporation
Inventor： William J. Lambert , Mathew J. Manusharow
CPC classification number: H05K1/116 , H05K1/0234 , H05K1/115 , H05K1/181 , H05K3/0047 , H05K3/32 , H05K3/4069 , H05K3/4084 , H05K3/4644 , H05K2201/0329 , H05K2201/0391 , H05K2201/0776 , H05K2201/09627 , H05K2201/10015 , H05K2203/14
Abstract: Discussed generally herein are methods and devices for altering an effective series resistance (ESR) of a component. A device can include a substrate including electrical connection circuitry therein, a first via hole through a first surface of the substrate and contiguous with the electrical connection circuitry, a first conductive polymer with a resistance greater than a resistance of the electrical connection circuitry filling the first via hole, and a component electrically coupled to the first conductive polymer.
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Patent Agency Ranking
66.发明申请公开(公告)号：US20170135208A1
公开(公告)日：2017-05-11
申请号：US15342308
申请日：2016-11-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Doh Won JUNG , Se Yun KIM , Jong Wook ROH , Jongmin LEE , Sungwoo HWANG , Jinyoung HWANG , Chan KWAK
CPC classification number: H05K1/09 , B82Y30/00 , B82Y40/00 , C01G55/004 , C01P2002/72 , C01P2002/85 , C01P2004/03 , C01P2004/04 , C01P2004/24 , C01P2004/61 , C01P2006/40 , C08K3/22 , C09D1/00 , C09D5/24 , C09D7/70 , H05K1/0274 , H05K3/28 , H05K2201/026 , H05K2201/0302 , H05K2201/032 , H05K2201/0326 , H05K2201/0338 , H05K2201/0776 , H05K2201/10977 , Y10S977/755 , Y10S977/896 , Y10S977/932
Abstract: An electrical conductor includes a substrate; and a first conductive layer disposed on the substrate and including a plurality of metal oxide nanosheets, wherein adjacent metal oxide nanosheets of the plurality of metal oxide nanosheets contact to provide an electrically conductive path between the contacting metal oxide nanosheets, wherein the plurality of metal oxide nanosheets include an oxide of Re, V, Os, Ru, Ta, Ir, Nb, W, Ga, Mo, In, Cr, Rh, Mn, Co, Fe, or a combination thereof, and wherein the metal oxide nanosheets of the plurality of metal oxide nanosheets have an average lateral dimension of greater than or equal to about 1.1 micrometers. Also an electronic device including the electrical conductor, and a method of preparing the electrical conductor.
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公开(公告)号：US20150107884A1
公开(公告)日：2015-04-23
申请号：US14391748
申请日：2013-02-28
Applicant: KABUSHIKI KAISHA NIHON MICRONICS
Inventor： Tatsuo Inoue , Takayasu Sugai , Toshiyuki Kudo , Toshinori Omori
CPC classification number: H05K1/0298 , H05K1/0233 , H05K1/0242 , H05K1/025 , H05K1/09 , H05K3/46 , H05K2201/0154 , H05K2201/0338 , H05K2201/0391 , H05K2201/0776 , H05K2201/0792 , H05K2201/083 , Y10T29/49155
Abstract: The object of the present invention is to provide a multi-layer wiring board which is easy to adjust the characteristic impedance and is able to adapt to the narrow-pitch tendency of terminals, and a process for manufacturing the same.The present invention attain the object by providing a multi-layer wiring board, in which more than one wiring layers are stacked on a substrate with an insulating layer between them, wherein a wire formed in the wiring layer has a double layered structure consists of a first layer and a second layer, and said first layer is made of a first conductive material and said second layer is made of a second conductive material having relative magnetic permeability larger than that of the first conductive material, thereby the characteristic impedance of said wire is adjusted to a value closer to 50 ohm than that of a wire which has the same thickness as of said wire having the double layered structure, and is made of said first conductive material only, and a process for manufacturing the same.
Abstract translation: 本发明的目的是提供一种容易调节特性阻抗并能够适应端子的窄倾斜趋势的多层布线板及其制造方法。 本发明的目的在于提供一种多层布线基板，其中多个布线层层叠在基板之间，在它们之间具有绝缘层，其中形成在布线层中的布线具有双层结构， 第一层和第二层，并且所述第一层由第一导电材料制成，并且所述第二层由具有比第一导电材料的相对导磁率大的相对磁导率的第二导电材料制成，由此所述导线的特征阻抗 调整为比具有与具有双层结构的所述线具有相同厚度的导线的接近50欧姆的值，并且仅由所述第一导电材料制成，及其制造方法。
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公开(公告)号：US20150086789A1
公开(公告)日：2015-03-26
申请号：US14377122
申请日：2013-05-31
Applicant: NITTO DENKO CORPORATION
Inventor： Daisuke Kajihara , Tomotake Nashiki , Motoki Haishi
CPC classification number: H05K1/0213 , C23C14/086 , G06F3/041 , H05K1/0274 , H05K1/032 , H05K1/0326 , H05K1/09 , H05K3/16 , H05K3/22 , H05K2201/0145 , H05K2201/0158 , H05K2201/0326 , H05K2201/0776 , H05K2203/1194 , Y10T428/31507 , Y10T428/31786 , Y10T428/31938
Abstract: A transparent conductive film includes a film base and a polycrystalline layer of indium tin oxide formed on the film base. The polycrystalline layer has a thickness of 10 nm to 30 nm, an average value of gain size of 180 nm to 270 nm, and a carrier density of greater than 6×1020/cm3 and less than or equal to 9×1020/cm3.
Abstract translation: 透明导电膜包括在基底上形成的膜基底和氧化铟锡的多晶层。 多晶层的厚度为10nm至30nm，增益尺寸的平均值为180nm至270nm，载流子密度大于6×1020 / cm3，小于或等于9×1020 / cm3。
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公开(公告)号：JP6272745B2
公开(公告)日：2018-01-31
申请号：JP2014218673
申请日：2014-10-27
Applicant: ソニー・オリンパスメディカルソリューションズ株式会社
Inventor： 菅野 清貴
CPC classification number: H01Q1/2283 , A61B1/04 , A61N1/37229 , G02B23/24 , H01Q21/28 , H04N5/225 , H05K1/0215 , H05K1/185 , H05K2201/0776
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70.发明专利導電性透明基板の製造方法および導電性透明基板（ＭＥＴＨＯＤ ＦＯＲ ＭＡＫＩＮＧ ＣＯＮＤＵＣＴＩＶＥ ＴＲＡＮＳＰＡＲＥＮＴ ＳＵＢＳＴＲＡＴＥ ＡＮＤ ＣＯＮＤＵＣＴＩＶＥ ＴＲＡＮＳＰＡＲＥＮＴ ＳＵＢＳＴＲＡＴＥ） 审中-公开制备和导电透明基板的导电性透明基板（METHOD FOR MAKING导电透明基板和导电性的透明基板）
公开(公告)号：JP2016531342A
公开(公告)日：2016-10-06
申请号：JP2016523671
申请日：2014-07-07
Inventor： クヮン−チョン チュン， , クヮン−チョン チュン， , ジ−フン ヨ， , ジ−フン ヨ， , ジョンキ ソン， , ジョンキ ソン， , ビュン フン キム， , ビュン フン キム， , ナン−ブ チョ， , ナン−ブ チョ， , ミュン−ボン ヨ， , ミュン−ボン ヨ，
CPC classification number: H05K1/0274 , G06F3/041 , G06F2203/04103 , H01L51/445 , H05K1/0213 , H05K1/0289 , H05K1/0298 , H05K1/0306 , H05K1/032 , H05K1/034 , H05K1/0346 , H05K1/097 , H05K3/0026 , H05K3/06 , H05K3/067 , H05K3/12 , H05K3/1258 , H05K2201/0776 , Y02E10/549 , Y02P70/521
Abstract: 【課題】透過性に優れた導電性透明基板を高歩留まりの工程によって製作することができる導電性透明基板の製造方法および導電性透明基板を提供すること。【解決手段】基板上に相互離隔されるように配列される複数の主電極を形成する主電極形成段階と、複数の主電極が互いに電気的に断絶される複数のグループ電極にグループ化されるように、2つ以上の主電極を電気的に連結する連結電極を形成する連結電極形成段階を含むことを特徴とする導電性透明基板の製造方法。【選択図】図1
Abstract translation: 提供一种制造方法和导电性透明基板优良导电性透明基板磁导率的导电性可以通过高产率透明衬底的工艺来制造。 多个形成工序，其被布置为彼此的基板间隔开的主电极的步骤主电极被分成多个组的电极，其中多个主电极的电相互断开 作为用于制备导电透明基板的方法，其特征在于：它包括用于电连接两个或更多个主电极上形成连接电极的连接电极形成工序。 点域1
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