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    Semiconductor device and manufacturing method for the same
    74.
    发明公开
    Semiconductor device and manufacturing method for the same 审中-公开
    Halbleitervorrichtung und Herstellungsverfahrendafür

    公开(公告)号：EP2131395A1

    公开(公告)日：2009-12-09

    申请号：EP09170937.8

    申请日：2003-08-20

    Applicant: Fujitsu Microelectronics Limited

    Inventor： Ariyoshi, Junichi ,  Torii, Satoshi

    IPC: H01L27/105 ,  H01L27/088 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/283

    CPC classification number: H01L27/11526 ,  H01L21/76897 ,  H01L27/105 ,  H01L27/11546 ,  H01L29/665 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: On a semiconductor substrate (30) having a gate electrode (32) and an LDD layer (33) formed thereon, an SiN film (34) to be a silicide block is formed. An opening (34a) communicating with the LDD layer (33) is provided for the SiN film (34). Impurities are introduced into the LDD layer (33) through the opening (34a) to form a source/drain layer (33a), and the surface thereof is silicided to form a silicide film (36a). Next, an interlayer insulation film (37) of SiO 2 is formed and then etched under a condition of an etching rate of SiO 2 higher than that of SiN to form a contact hole (37h) reaching the LDD layer (33) from the upper surface of the interlayer insulation film (37) via the opening (34a).

    Abstract translation: 在其上形成有栅极（32）和LDD层（33）的半导体衬底（30）上形成作为硅化物块的SiN膜（34）。 为SiN膜（34）提供与LDD层（33）连通的开口（34a）。 通过开口（34a）将杂质引入LDD层（33），形成源/漏层（33a），其表面被硅化以形成硅化物膜（36a）。 接下来，形成SiO 2的层间绝缘膜（37），然后在SiO 2的蚀刻速率高于SiN的蚀刻速率的条件下进行蚀刻，形成从上部到达LDD层（33）的接触孔（37h） 经由开口（34a）的层间绝缘膜（37）的表面。

    Communication synchronization apparatus/program
    75.
    发明公开
    Communication synchronization apparatus/program 审中-公开
    通信同步装置/程序

    公开(公告)号：EP2120357A1

    公开(公告)日：2009-11-18

    申请号：EP09167399.6

    申请日：2000-03-23

    Applicant: Fujitsu Microelectronics Limited

    Inventor： Kuroiwa, Koichi ,  Kanasugi, Masami ,  Hikita, Mahiro ,  Taniguchi, Shoji

    IPC: H04B1/707

    CPC classification number: H04W48/16 ,  H04B1/7075 ,  H04B1/70755 ,  H04B1/7083 ,  H04B1/709 ,  H04B2201/70702

    Abstract: A communication synchronization apparatus with which a station detects, for each slot in a predetermined unit, a correlation value between an input signal and a spreading code generated by the station itself, the detection process for the correlation value is performed over several slots, the correlation values obtained in the slots are integrated to detect a correlation peak value, and thereby a synchronization point of said input signal is detected, said apparatus comprising a controlling section for ending the integration when the number of paths, at which a power integration value for converting the detected correlation value into a power value has reached a reference set value, reaches a path count set value.

    Abstract translation: 一种通信同步装置，利用该通信同步装置，对于预定单元中的每个时隙，检测输入信号与由该站自身产生的扩展码之间的相关值，对相关值的检测处理在多个时隙上执行，相关 对在时隙中获得的值进行积分以检测相关峰值，从而检测所述输入信号的同步点，所述设备包括控制部分，用于在路径的数量达到用于转换的功率积分值 检测到的相关值转换成功率值已达到参考设定值，达到路径计数设定值。

    Computer bus configuration and input/output buffer
    77.
    发明授权
    Computer bus configuration and input/output buffer 失效
    Rechnerbuskonfiguration和输入/输出驱动器

    公开(公告)号：EP1308847B1

    公开(公告)日：2009-11-04

    申请号：EP03000313.1

    申请日：1996-11-20

    Applicant: Fujitsu Microelectronics Limited

    Inventor： Taguchi, Masao, c/o Fujitsu Limited

    IPC: G06F13/40 ,  H03K19/0175

    CPC classification number: G11C7/1057 ,  G06F13/4077 ,  G06F13/4086 ,  G11C7/1051 ,  G11C2207/2227 ,  H03K19/0016 ,  H03K19/017545 ,  H03K19/018585 ,  Y02D10/14 ,  Y02D10/151

    Abstract: An input buffer circuit is disclosed which is connected to a bus for receiving signals from the bus. The input buffer circuit comprises a first buffer (40, 43) for receiving the signals, the first buffer (40, 43) being operable in a first mode in which the signals are transmitted on the bus (10) at a first frequency, a second buffer (41, 44) for receiving the signals, the second buffer (41, 44) being operable in a second mode in which said signals are transmitted on said bus (10) at a second frequency lower than the first frequency, and means (24) for providing one of an output of the first buffer (40, 43) and an output of the second buffer (41, 44) to an internal circuit. The power consumption of the second buffer (41, 44) during operation thereof is lower than power consumption of the first buffer (40, 43) during operation thereof. A corresponding output buffer circuit is also disclosed.

    A/D conversion circuit
    78.
    发明公开
    A/D conversion circuit 有权
    AD Wandlerschaltung

    公开(公告)号：EP2110952A1

    公开(公告)日：2009-10-21

    申请号：EP09164948.3

    申请日：2003-10-21

    Applicant: Fujitsu Microelectronics Limited

    Inventor： Shimizu, Yoshiaki ,  Suzuki, Hisao ,  Ito, Kenji ,  Kijima, Masashi

    IPC: H03M1/16 ,  H03M1/36

    CPC classification number: H03M1/0675 ,  H03M1/08 ,  H03M1/165 ,  H03M1/168 ,  H03M1/366 ,  H03M1/42 ,  H03M1/765

    Abstract: A current-mode multi-residue multi- stage ADC ( fig. 14 and 15 ), each stage being a 2-bit current flash converter. The first stage (32) generates (N20-N23) four copies of the input current and subtract to them four reference currents (I20-I23) corresponding to the four quantization levels of the first stage. The currents which are result of the subtraction are input to comparators (C01-C03) and an encoder (35) for generating the digital output (D3-D2) of the first stage and each to a corresponding one of second stage units (32a-32d) for lower-bit conversion. Each of the second stage unit has the same structure as the first stage.

    Abstract translation: 电流模式多残留多级ADC（图14和15），每级是2位电流闪存转换器。 第一级（32）产生输入电流的四个副本（N20-N23），并将与第一级的四个量化级相对应的四个参考电流（I20-I23）相减。 作为减法结果的电流被输入到比较器（C01-C03）和用于产生第一级的数字输出（D3-D2）的编码器（35），并且每个到第二级单元（32a- 32d）用于低位转换。 第二级单元具有与第一级相同的结构。

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