Dielectric resonator and filter
    71.
    发明专利

    公开(公告)号:GB2284942A

    公开(公告)日:1995-06-21

    申请号:GB9425244

    申请日:1994-12-14

    Abstract: A dielectric resonator comprises a dielectric block 301 with a first electrode 305 formed on a first surface 302 and a second electrode 304 formed within an inner conductive hole 303 extending from the surface opposite the first surface 302, towards but not reaching the first surface 302, such that the first and second electrodes 304, 305 face each other to form a coupling capacitor and a conductive layer formed on one or more of the remaining surfaces. The resonators may be combined to form a filter arrangement. The filter may include window and groove arrangements to adjust the coupling between the resonators. The inner conductive hole 303 may have a circular, elliptical or quadrilateral cross sectional shape. The first electrode 305 may extend to an edge of the dielectric block 301 to form a connection terminal allowing direct surface mounting on to a circuit board.

    Multiplier
    72.
    发明专利

    公开(公告)号:GB2261093B

    公开(公告)日:1995-06-21

    申请号:GB9213382

    申请日:1992-06-24

    Inventor: HAN IL SONG

    Abstract: A MOSFET controlling multiplier for obtaining the precise function of the operational multiplication by offsetting the offset voltage of MOSFET to remove the non-linear current of MOSFET, utilizing symmetrical voltage sources and a current mirror circuit is disclosed. The MOSFET controlling multiplier utilizes a MOSFET linear means for linearly varying the output current I to a node A in accordance with an input voltage from an input voltage source Vg and a symmetrical input voltage from voltage sources Vx and -Vx. The input voltage from the input voltage source Vg is operatively associated with the symmetrical input voltage from the voltage sources Vx and -Vx. An impedance element Z outputs a voltage Vo, with the impedance element Z being connected to the node A of the MOSFET linear means and the ground.

    Bipolar transistor fabrication
    74.
    发明专利

    公开(公告)号:GB9425603D0

    公开(公告)日:1995-02-15

    申请号:GB9425603

    申请日:1994-12-19

    Abstract: Disclosed is a fabrication of a bipolar transistor using an enhanced trench isolation so as to improve integration and performance thereof, comprising the steps of sequentially etching back portions corresponding to a trench using a trench forming mask to a predetermined depth of the buried collector to form the trench; filling an isolation insulating layer into the trench; polishing the isolation insulating layer up to a surface of the silicon oxide layer; sequentially forming a second insulating layer on the isolating insulating layer and the silicon oxide layer; removing the first polysilicon layer and the first insulating layer formed on an inactive region other than an active region defined by the trench; thermal-oxidizing the collector layer formed on the inactive region to form a thermal oxide layer; removing the second insulating layer and sequentially forming a third polysilicon, a third insulating layer and a second nitride layer; etching back layers formed on a portion of the first insulating layer to form an opening in the active region; forming a first side wall on both edges of the opening and removing the first insulating layer; forming an intrinsic base at a region where the first insulating layer is removed to electrically connect the intrinsic base with an extrinsic base in self-alignment; forming a second side wall on both sides of the first side wall; and forming an emitter layer on the intrinsic base.

    76.
    发明专利
    未知

    公开(公告)号:AT398010B

    公开(公告)日:1994-08-25

    申请号:AT144692

    申请日:1992-07-15

    Abstract: A MOSFET controlling multiplier for obtaining the precise function of the operational multiplication by offsetting the offset voltage of MOSFET to remove the non-linear current of MOSFET, utilizing symmetrical voltage sources and a current mirror circuit is disclosed. The MOSFET controlling multiplier utilizes a MOSFET linear means for linearly varying the output current I to a node A in accordance with an input voltage from an input voltage source Vg and a symmetrical input voltage from voltage sources Vx and -Vx. The input voltage from the input voltage source Vg is operatively associated with the symmetrical input voltage from the voltage sources Vx and -Vx. An impedance element Z outputs a voltage Vo, with the impedance element Z being connected to the node A of the MOSFET linear means and the ground.

    Coin Treatment Apparatus
    78.
    发明专利

    公开(公告)号:CA2115838A1

    公开(公告)日:1994-01-26

    申请号:CA2115838

    申请日:1993-06-18

    Abstract: PCT No. PCT/KR93/00050 Sec. 371 Date Jun. 27, 1994 Sec. 102(e) Date Jun. 27, 1994 PCT Filed Jun. 18, 1993 PCT Pub. No. WO94/00828 PCT Pub. Date Jan. 6, 1994A coin treatment apparatus is disclosed that includes structure for selecting the inserted coins based upon their size, in accordance with their specific currency units, and transferring the coins to a receiving space. Once in the receiving space, coins of the correct currency unit are moved to their respective receiving containers within a receiving box. Coins that are not of the correct currency unit are transferred to a separate receiving space and discharged from the apparatus.

    79.
    发明专利
    未知

    公开(公告)号:ATA144592A

    公开(公告)日:1993-08-15

    申请号:AT144592

    申请日:1992-07-15

    Abstract: A MOSFET analog multiplier with a variable resistive MOSFET linear means for linearly varying output current I depending upon a symmetrical input voltage from voltage sources V2 and -V2 and an input voltage from an input voltage source V1 operatively associated with the symmetrical input voltage from the voltage source V2 and -V2, with the variable resistive MOSFET linear means having a node A to output the varied output current I therethrough is disclosed. An operational amplifying unit for amplifying the linearly varied output current I and which includes an operational amplifier U with an inverting input terminal connected to the node A of the MOSFET linear means, a non-inverting input terminal connected to ground, and an output terminal. The operational amplifying unit further includes a feedback element Z connected between the inverting input terminal and the output terminal of the operational amplifier U, where in use the output terminal outputs a voltage Vo.

    MOFSET ANALOG MULTIPLIER.
    80.
    发明专利

    公开(公告)号:GR920100398A

    公开(公告)日:1993-07-30

    申请号:GR92100398

    申请日:1992-09-23

    Inventor: IL SONG HAN

    Abstract: A MOSFET analog multiplier with a variable resistive MOSFET linear means for linearly varying output current I depending upon a symmetrical input voltage from voltage sources V2 and -V2 and an input voltage from an input voltage source V1 operatively associated with the symmetrical input voltage from the voltage source V2 and -V2, with the variable resistive MOSFET linear means having a node A to output the varied output current I therethrough is disclosed. An operational amplifying unit for amplifying the linearly varied output current I and which includes an operational amplifier U with an inverting input terminal connected to the node A of the MOSFET linear means, a non-inverting input terminal connected to ground, and an output terminal. The operational amplifying unit further includes a feedback element Z connected between the inverting input terminal and the output terminal of the operational amplifier U, where in use the output terminal outputs a voltage Vo.

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