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公开(公告)号:FR2800511A1
公开(公告)日:2001-05-04
申请号:FR9913753
申请日:1999-10-28
Applicant: PIXTECH SA
Abstract: The flat screen display has a cathode (1) with field effect electronic transmission (2). There is an anode (5) illuminated by the cathode, together with an extraction grid (3). There is a grid (20) permeable to electronic bombardment which is polarised to prevent ion parasitics.
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公开(公告)号:FR2799575A1
公开(公告)日:2001-04-13
申请号:FR9912843
申请日:1999-10-08
Applicant: PIXTECH SA
Inventor: OULES CHATON CATHERINE
Abstract: The anode manufacture technique forms anode conductor tracks (9b,9r) on a substrate perpendicular to a first feed track (13) with a second feed track (15) parallel to the first. Interconnections to the second feed track are made by wire conductors (20) above the first feed track. Connection is followed by encapsulation.
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公开(公告)号:FR2790329A1
公开(公告)日:2000-09-01
申请号:FR9902654
申请日:1999-02-26
Applicant: PIXTECH SA
Inventor: BANCAL BERNARD
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公开(公告)号:FR2785719A1
公开(公告)日:2000-05-12
申请号:FR9814226
申请日:1998-11-09
Applicant: PIXTECH SA
Inventor: VALERO REMI
Abstract: Formation of zinc oxide or indium oxide layer on the surface of a luminophor deposited on a substrate involves adding the luminophor grains to an aqueous solution containing dissolved zinc nitrate or indium nitrate, polyvinyl alcohol (serigraphic binder) and antifoaming agent in water, deposition, and annealing. 1-0.6g of the nitrate and 6-10g of the luminophor are dissolved in 10g of the solution. The luminophor is selected from the following: Gd2O2S:Tb, Y2SiO5:Tb, Y2SiO5:Ce, Y2O3:Eu and ZnO:Zn. Annealing is carried out at 400-500 degrees C for several hours.
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公开(公告)号:FR2770338B1
公开(公告)日:2000-01-14
申请号:FR9713592
申请日:1997-10-24
Applicant: PIXTECH SA
Inventor: JAGER AXEL , ROMMEVEAUX PHILIPPE
Abstract: The intermediate section is opaque and the shape of the individual symbols is adjusted to remove the moire distortion effect.
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公开(公告)号:FR2769114A1
公开(公告)日:1999-04-02
申请号:FR9712392
申请日:1997-09-30
Applicant: PIXTECH SA
Inventor: BANCAL BERNARD , PEYRE JEAN FRANCOIS , PEYRON PHILIPPE
Abstract: The display screen has a micro-point cathode emitting electrons and an associated grid to extract the electrons. The cathode/grid is formed from conductive rows (15') which can be addressed sequentially and perpendicular columns (14') that can be addressed individually and simultaneously during addressing of the rows. A return electrode (30) set to a positive potential is connected via a resistance to each grid or cathode row.
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公开(公告)号:DE69507101D1
公开(公告)日:1999-02-18
申请号:DE69507101
申请日:1995-09-25
Applicant: PIXTECH SA
Inventor: PEYRE JEAN-FRANCOIS , COURREGES FRANCIS
IPC: G09G3/22 , H01J9/14 , H01J29/10 , H01J29/28 , H01J29/96 , H01J31/12 , H04N9/30 , H01J31/15 , H01J29/08
Abstract: The anode flat screen connecting structure has parallel cathode strips (9r,9g,9b) for each colour, above luminous micropoints. The strips are connected to solid resistances (22). The other end of the resistance blocks is connected to parallel tracks (21r,21g,21b) which form the voltage rails. There is an isolation layer (23) to isolate the voltage rails from the resistors. Each resistor has an opening (24r,24g) at one end and a second opening (25b,25g) at the other end.
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公开(公告)号:FR2766964A1
公开(公告)日:1999-02-05
申请号:FR9709917
申请日:1997-07-29
Applicant: PIXTECH SA
Inventor: MOUGIN STEPHANE , CHASSAGNE PASCAL
IPC: H01J9/24 , H01J5/02 , H01J5/24 , H01J9/26 , H01J29/86 , H01J29/94 , H01J31/12 , H01J9/40 , H01J9/38
Abstract: The vacuum assembly method in an oven assembles two parallel screens (1,4) in an internal space (6). The peripheral sealing is effected in two steps. In the first step, a first sealing joint (5) is sealed, maintaining open a second hole (13) of communication with the internal space. In a second step, a closure element (16) seals a second sealing unit (15) sealed at a second temperature lower than the first sealing temperature.
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公开(公告)号:FR2750785B1
公开(公告)日:1998-11-06
申请号:FR9608487
申请日:1996-07-02
Applicant: PIXTECH SA
Inventor: BANCAL BERNARD
Abstract: The grid is biased to a regeneration potential distinctly greater than the nominal potential and the cathode is biased to a nominal potential corresponding to a maximum emission. The rows (L) of the grid are addressed in sequence during a nominal time during which the cathode columns (K) are individually addressed. At least one row, perhaps all, of the grid is biased to a the regeneration potential and all the cathode columns are at the maximum emission potential for a regeneration time distinctly greater than the nominal time. The rows are addressed by a pulsed signal (Hreg) whose mark is distinctly longer than the nominal time and distinctly shorter than the space time to avoid overheating.
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公开(公告)号:FR2761523A1
公开(公告)日:1998-10-02
申请号:FR9704096
申请日:1997-03-28
Applicant: PIXTECH SA
Inventor: PEPI RICHARD
Abstract: The flat screen display panel consists of two parallel plates defining between them an inter-electrode space. At least one of the parallel plates comprises small projecting tabs (20) in the active region. These tabs project a distance which is significantly less than the thickness of the space separating the two parallel plates. The tabs are grouped in either groups of three or four, and in such a group define a seating for a ball (23). The tabs may be aligned on the insulating lines which separate adjacent pixels of the screen, and may be in two pairs aligned along perpendicular axes. The ball serves as a spacer, defining the inter-electrode space and ensuring a uniform separation.
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