公开(公告)号：SG11201501617YA

公开(公告)日：2015-04-29

申请号：SG11201501617Y

申请日：2013-08-09

Applicant: R&D CIRCUITS INC

Inventor： DAN TURPUSEEMA ,  JAMES V RUSSELL

IPC: H05K3/06 ,  H01L21/02 ,  H05K1/02

公开(公告)号：SG10201405623QA

公开(公告)日：2014-11-27

申请号：SG10201405623Q

申请日：2010-01-08

Applicant: R&D CIRCUITS INC

Inventor： RUSSELL JAMES V

公开(公告)号：SG179125A1

公开(公告)日：2012-04-27

申请号：SG2012017810

申请日：2010-01-08

Applicant: R & D CIRCUITS INC

Inventor： RUSSELL JAMES V

Abstract: The present disclosure provides for attaching and embedding a capacitance or a resistance directly in an adaptor board or an interposer board that is then connected to the main circuit board. The adaptor board can be connected to the main circuit board by soldering, electrically connecting it by a conductive elastomer connection, spring pins or by any other way that is known in the art.

公开(公告)号：SG178121A1

公开(公告)日：2012-03-29

申请号：SG2012005781

申请日：2010-01-08

Applicant: R & D CIRCUITS INC

Inventor： RUSSELL JAMES V

Abstract: The present disclosure relates to embedding a power modification component such as a capacitance or a resistance inside of pads that are located to extend over and beyond the vias of the PCB so that a portion of the pad containing the embedded capacitance or resistance is located beyond where the vias or blinds are located. Each of the pads will include an opening that is located over a given one of the vias or blinds to permit that via to conduct through the opening. In this way the capacitance and the resistance will have a closer contact point the electrical component.

公开(公告)号：US12153084B2

公开(公告)日：2024-11-26

申请号：US17173441

申请日：2021-02-11

Applicant: R & D Circuits, Inc.

Inventor： Donald Eric Thompson ,  Thomas Smith

IPC: G01R31/28 ,  G01R31/70 ,  H05K3/00 ,  H05K3/42

Abstract: A method for detecting failed back-drills in PCBs in the process of fabricating a PCB so that the failed back-drill can be screened out or repaired. short to ground connection is added for every back-drill via that will be cut when the back-drill removes the via stub. If the back-drill is bad or failed the short to ground will fail the subsequent electrical tests. The PCB can be repaired by re-drilling the hole or via. Failed back-drills may be detected in the manufacturing stage using standard equipment and test procedures. This process creates a simple pass-fail measurement that uses an existing common test process to catch failed back drills in the PCB fabrication facility. This allows for easy and cost-effective repair and guarantees back-drill failures do not pass into the field.

公开(公告)号：US20180068867A1

公开(公告)日：2018-03-08

申请号：US15688238

申请日：2017-08-28

Applicant: R&D CIRCUITS, INC.

Inventor： Donald Thompson ,  Cosimo Cantatore

IPC: H01L21/48 ,  H01R12/70 ,  H01R12/52 ,  H01R13/11 ,  H01R13/24

CPC classification number: H01L21/486 ,  B33Y80/00 ,  G01R1/0483 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2224/16227 ,  H01L2224/1623 ,  H01L2224/16235 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01R12/52 ,  H01R12/7082 ,  H01R13/112 ,  H01R13/2414 ,  H05K1/092 ,  H05K3/4069 ,  H05K7/1061 ,  H05K2203/107 ,  H05K2203/1131

Abstract: The present invention provides for a structure and a mechanism by which by utilizing additive manufacturing processes electrical connections are created that connect the top and bottom of a block in a customizable pattern. Specifically connection points can be created on the surface of the block and route them to alternate locations transforming the original pattern to a smaller, larger, or alternate pattern.

公开(公告)号：US10559476B2

公开(公告)日：2020-02-11

申请号：US15688238

申请日：2017-08-28

Applicant: R&D Circuits, Inc.

Inventor： Donald Thompson ,  Cosimo Cantatore

IPC: H01L21/48 ,  H01R12/52 ,  H01R12/70 ,  H01R13/11 ,  H01R13/24

Abstract: The present invention provides for a structure and a mechanism by which by utilizing additive manufacturing processes electrical connections are created that connect the top and bottom of a block in a customizable pattern. Specifically connection points can be created on the surface of the block and route them to alternate locations transforming the original pattern to a smaller, larger, or alternate pattern.

公开(公告)号：US10257930B2

公开(公告)日：2019-04-09

申请号：US15189435

申请日：2016-06-22

Applicant: R&D CIRCUITS, INC.

Inventor： Thomas P Warwick ,  Dhananjaya Trupuseema ,  James V Russell

IPC: H01R43/00 ,  H05K1/11 ,  H05K3/40 ,  H05K3/10 ,  H05K3/32 ,  H05K1/09 ,  H05K1/02 ,  H05K1/18

Abstract: The present invention provides for a method and structure for forming three-dimensionally routed dielectric wires between discrete points on the two or more parallel circuit planes. The wires may be freely routed in three-dimensional space as to create the most efficient routing between the two arbitrarily defined points on the two or more parallel circuit planes. Metalizing the outer surfaces of these three dimensional dielectric wires electrically coupling the discrete wires to their respective discrete contact points. Two or more of these wires may be in intimate contact to one another electrically coupling to each other as well as to two or more discrete contact pads. These electrically coupled contact pads may be on opposite sides or on the same side of the structure and the formed metalized wires may originate on one side and terminate on the other or originate and terminate from the same side.

公开(公告)号：US20170374739A1

公开(公告)日：2017-12-28

申请号：US15189435

申请日：2016-06-22

Applicant: R&D CIRCUITS, INC.

Inventor： THOMAS P. WARWICK ,  DHANANJAYA TRUPUSEEMA ,  JAMES V. RUSSELL

IPC: H05K1/11 ,  H05K1/09 ,  H05K1/18 ,  H05K1/02 ,  H05K3/10 ,  H05K3/32 ,  H05K3/40

CPC classification number: H05K1/111 ,  H01L21/486 ,  H01L23/49827 ,  H01R13/2435 ,  H05K1/0251 ,  H05K1/0296 ,  H05K1/09 ,  H05K1/118 ,  H05K1/18 ,  H05K3/10 ,  H05K3/32 ,  H05K3/368 ,  H05K3/4007 ,  H05K3/4038 ,  H05K3/4046 ,  H05K2201/10015 ,  H05K2201/10022 ,  H05K2201/1003 ,  H05K2201/10378

Abstract: The present invention provides for a method and structure for forming three-dimensionally routed dielectric wires between discrete points on the two or more parallel circuit planes. The wires may be freely routed in three-dimensional space as to create the most efficient routing between the two arbitrarily defined points on the two or more parallel circuit planes. Metalizing the outer surfaces of these three dimensional dielectric wires electrically coupling the discrete wires to their respective discrete contact points. Two or more of these wires may be in intimate contact to one another electrically coupling to each other as well as to two or more discrete contact pads. These electrically coupled contact pads may be on opposite sides or on the same side of the structure and the formed metalized wires may originate on one side and terminate on the other or originate and terminate from the same side

公开(公告)号：US20220252660A1

公开(公告)日：2022-08-11

申请号：US17173441

申请日：2021-02-11

Applicant: R & D Circuits, Inc.

Inventor： Donald Eric Thompson ,  Thomas Smith

IPC: G01R31/28 ,  G01R31/70 ,  H05K3/42 ,  H05K3/00

Abstract: The present invention provides a method for detecting failed back-drills in PCBs in the process of fabricating a PCB so that the failed back-drill can be screened out or repaired. The present invention accomplishes this by adding a short to ground connection for every back-drill via that will be cut when the back-drill removes the via stub. If the back-drill is bad or failed the short to ground will fail the subsequent electrical tests. The PCB can be repaired by re-drilling the hole or via. The present invention allows for detecting failed back-drills with easy detection in the manufacturing stage using standard equipment and test procedures. This process creates a simple pass-fail measurement that uses an existing common test process to catch failed back drills in the PCB fabrication facility. This allows for easy and cost-effective repair and guarantees back-drill failures do not pass into the field.