公开(公告)号：EP0587401A3

公开(公告)日：1996-03-06

申请号：EP93307036.9

申请日：1993-09-07

Applicant: SGS-Thomson Microelectronics Limited

Inventor： Wyborn, Graeme Michael ,  McGee, Christopher ,  Nicholls, Howard Charles

IPC: H01L21/3205 ,  H01L21/90 ,  C23C16/14

CPC classification number: H01L21/28556 ,  H01L21/28562 ,  H01L21/32051 ,  H01L21/76877 ,  H01L21/76879

Abstract: A method of fabricating a tungsten contact in a semiconductor device, the method including the steps of: (a) providing a silicon wafer structure including a dielectric layer and an underlying layer selected from a semiconductor or electrically conductive material, the dielectric layer being patterned to expose a contact portion of the underlying layer; and (b) depositing by chemical vapour deposition a tungsten layer over the dielectric layer and the contact portion, the deposition being carried out by reaction of a tungsten- containing component and a reducing agent which are introduced into the vicinity of the silicon wafer structure, the deposition step having a first phase in which the process conditions are controlled to form a seed layer of tungsten on the dielectric layer and a second phase in which the process conditions are modified from the first phase to form a blanket tungsten layer over the seed layer which acts as an adhesion layer between the dielectric layer and the blanket tungsten layer. The invention also provides a semiconductor device incorporating a tungsten contact which is disposed in a contact hole of a dielectric layer, the tungsten contact including a seed layer of tungsten which extends over the dielectric layer surface and an overlying layer of blanket tungsten.

公开(公告)号：EP0645881A1

公开(公告)日：1995-03-29

申请号：EP94306135.8

申请日：1994-08-19

Applicant: SGS-Thomson Microelectronics Limited

Inventor： Horsfall, Wayne Leslie ,  Shipton, Gary

IPC: H03D3/24

CPC classification number: H03D3/244

Abstract: A method of demodulating an FM carrier wave and an FM demodulation circuit are described which use a phase locked loop. The phase locked loop is tuned to a selected carrier wave frequency including the step of selecting a setting of the variable gain circuit in the phase locked loop to select a desired loop gain.

Abstract translation: 描述了使用锁相环解调FM载波和FM解调电路的方法。 锁相环被调谐到选定的载波频率，包括在锁相环中选择可变增益电路的设置以选择期望的环路增益的步骤。

公开(公告)号：EP0629068A1

公开(公告)日：1994-12-14

申请号：EP94304142.6

申请日：1994-06-08

Applicant: SGS-Thomson Microelectronics Limited

Inventor： Walker, Christopher Paul Hulme

IPC: H04L25/49 ,  H04L1/00 ,  H04J3/06

CPC classification number: H04L1/0057 ,  H04J3/0605 ,  H04J3/0632 ,  H04L1/0083 ,  H04L1/246 ,  H04L7/046 ,  H04L25/4908

Abstract: An encoding scheme relies on a d.c. balanced code wherein each message to be transmitted is sent as a plurality of symbols, each symbol having six bits, three ones and three zeros. Out of the twenty combinations of balanced six-bit codes, two codes are reserved to operate as control tokens, being 010101 and 101010. Because of the particular format of the symbols, control tokens can be easily detected. Furthermore, they can be combined in longer bit sequences for use as initialisation and disconnect sequences.

Abstract translation: 编码方案依赖于直流 平衡代码，其中要发送的每个消息作为多个符号发送，每个符号具有六个位，三个和三个零。 在平衡的六位代码的二十种组合中，两个代码被保留作为控制令牌来操作，为010101和101010.由于符号的特定格式，可以容易地检测到控制令牌。 此外，它们可以以更长的比特序列组合用作初始化和断开序列。

公开(公告)号：EP0492968A3

公开(公告)日：1994-11-30

申请号：EP91311769.3

申请日：1991-12-18

Applicant: SGS-Thomson Microelectronics Limited

Inventor： Azmoodeh, Saeid ,  Boffey, Peter Malcolm Keith ,  Forsyth, Richard Matthew ,  Parsons, Brian Jeremy

IPC: G06F9/38

CPC classification number: G06F9/3822 ,  G06F9/3824 ,  G06F9/3853 ,  G06F9/3885

Abstract: Computer appratus includes an instruction execution unit (13) having a plurality of functional units (14,16) each arranged to execute at least part of an instruction and instruction issuing circuitry (10,12) for issuing simultaneously a group of separate compatible instructions to the execution unit (13) the circuitry (12) having means for classifying each instruction in dependence on the or each functional unit required for execution of that instruction and means for testing the classification of successive instructions and selecting a group which according to their classification are compatible for simultaneous issue to the execution unit (13) without conflicting demands on any function unit (14,16) in the execution unit.

公开(公告)号：EP0610064A2

公开(公告)日：1994-08-10

申请号：EP94300737.7

申请日：1994-02-01

Applicant: SGS-Thomson Microelectronics Limited

Inventor： Hall, Andrew Medlicott ,  Monk, Trevor Kenneth

IPC: H03K17/16 ,  G05F3/24

CPC classification number: H03K17/163 ,  G05F3/242

Abstract: A switching circuit for an FET transistor includes a controlled current circuit coupled to the gate of the FET. The input (36) to the controlled current circuit represents a desired rate of change of gate voltage of the FET and is generated by a circuit responsive to the average specific transconductance of two FETs (41,42) of similar specific transconductance operating at different drain current densities. Circuitry (51,52) is responsive to different gate voltages of the transistors (41,42) at the respective drain current densities to operate the signal (36).

Abstract translation: 用于FET晶体管的开关电路包括耦合到FET的栅极的受控电流电路。 受控电流电路的输入（36）表示FET的栅极电压的期望变化率，并且由响应于在不同漏极操作的具有类似特定跨导的两个FET（41,42）的平均特定跨导的电路 电流密度。 电路（51,52）响应于各个漏极电流密度处的晶体管（41,42）的不同栅极电压来操作信号（36）。

公开(公告)号：EP0518580A3

公开(公告)日：1994-04-27

申请号：EP92305211.2

申请日：1992-06-08

Applicant: SGS-Thomson Microelectronics Limited

Inventor： Bramley, Richard Gavin

IPC: H04N5/21

CPC classification number: H04N5/211

Abstract: Apparatus for filtering ghost signals from a video signal sequence comprises storage circuitry (14) for storing a representation of the reference signal, input circuitry (16) for inputting video signals from the video signal sequence, comparison circuitry (12) for comparing the stored representation of the reference signal with the reference signal received in the video signal sequence at said input circuitry thereby to detect ghosts, filter coefficient generating circuitry connected to said comparison circuitry to generate a frequency domain representation of filter coefficients dependent on ghost signals detected, a forward fourier transform pipeline (22) connected to said input circuitry (16) to form a frequency domain representation of data in the video signal sequence received by said input circuitry, product forming circuitry (35) for forming in the frequency domain a product of the filter coefficients with the frequency domain representation of the data in the video signal sequence, and an inverse fourier transform pipeline (45) connected to said product forming circuitry (35) for receiving said product and transforming it to provide an output in the time domain representing said video signal sequence from which detected ghost signals have been removed.

Abstract translation: 用于从视频信号序列中滤除幻像信号的设备包括：用于存储参考信号的表示的存储电路（14），用于从视频信号序列输入视频信号的输入电路（16），用于比较存储的表示 将所述参考信号与在所述输入电路中的视频信号序列中接收的参考信号进行比较，从而检测重影;连接到所述比较电路的滤波器系数产生电路，以根据检测到的重影信号产生滤波器系数的频域表示;前向傅立叶 连接到所述输入电路（16）的变换流水线（22），以形成由所述输入电路接收的视频信号序列中的数据的频域表示;产品形成电路（35），用于在频域中形成滤波器系数 其中视频信号中数据的频域表示为seque 以及连接到所述产品形成电路（35）的逆傅立叶变换流水线（45），用于接收所述产品并对其进行变换以在时域中提供代表所述视频信号序列的输出，所述视频信号序列从其中检测到的幻影信号已被去除。

公开(公告)号：EP0587400A2

公开(公告)日：1994-03-16

申请号：EP93307035.1

申请日：1993-09-07

Applicant: SGS-Thomson Microelectronics Limited

Inventor： Wyborn, Graeme Michael ,  Nicholls, Howard Charles

IPC: H01L21/90 ,  H01L23/522 ,  H01L21/3205 ,  H01L21/285

CPC classification number: H01L21/76838 ,  H01L23/5226 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of fabricating a semiconductor device incorporating a via and an interconnect layer of aluminium or aluminium alloy, the method comprising the steps of: (a) providing a silicon wafer structure; (b) forming an interconnect layer (2) of aluminium or aluminium alloy on the structure; (c) forming a capping layer (12) over the interconnect layer, the capping layer being composed of electrically conductive material; (d) forming a dielectric layer (14) on the capping layer; and (e) selectively depositing an electrically conductive contact (18) on the capping layer in a contact hole (16) of the dielectric layer thereby to form a via, the materials of the capping layer (12) and of the contact (18) being selected whereby after the contact has been deposited on the capping layer at the interface therebetween there is substantial absence of non-conductive compounds formed from the material of the capping layer. The invention also provides a semiconductor device including a via and an interconnect layer of aluminium or aluminium alloy, a capping layer of electrically conductive material which has been formed over the interconnect layer and an electrically conductive contact which has been selectively deposited on the capping layer thereby to form a via, the materials of the capping layer and of the contact being selected whereby at the interface therebetween there is substantial absence of non-conductive compounds formed from the material of the capping layer.

Abstract translation: 一种制造包含铝或铝合金的通孔和互连层的半导体器件的方法，所述方法包括以下步骤：（a）提供硅晶片结构; （b）在所述结构上形成铝或铝合金的互连层; （c）在所述互连层上形成覆盖层，所述覆盖层由导电材料构成; （d）在封盖层上形成电介质层; 和（e）在电介质层的接触孔中的覆盖层上选择性地沉积导电接触，从而形成通孔，从而选择覆盖层和接触层的材料，由此在接触已经沉积在覆盖层上之后 在它们之间的界面处，基本上不存在由覆盖层的材料形成的非导电化合物。 本发明还提供了一种半导体器件，其包括通孔和铝或铝合金的互连层，已经在互连层上形成的导电材料的覆盖层和已经选择性地沉积在覆盖层上的导电触点 为了形成通孔，所述覆盖层和接触层的材料被选择，由此在其间的界面处基本上不存在由覆盖层的材料形成的非导电化合物。

公开(公告)号：EP0523854A3

公开(公告)日：1993-07-28

申请号：EP92305478.7

申请日：1992-06-15

Applicant: SGS-Thomson Microelectronics Limited

Inventor： Cytera, Christopher ,  Hall, Andrew Medlicott

IPC: H03L7/099 ,  H03B5/24

CPC classification number: H03L7/0995 ,  H03B5/24 ,  H03B27/00 ,  H03B2200/0038 ,  H03B2200/0058 ,  H03B2200/0062 ,  H03B2200/0078 ,  H03B2201/02 ,  H03L1/00

Abstract: The oscillator comprises a plurality of differential amplication stages (10,12,14,16) each arranged to introduce a phase shift between its differential input signal and its differential output signal such that the total phase shift introduced by the stages is 360 o . In this way an oscillating signal is produced at the output of each stage. Because each stage receives and supplies difference signals, any changes in the power supply of the stages affect both inputs or outputs in the same way so that the effect on the differential signal is minimal. The circuit thus provides a reduction of the effect of power supply noise. The oscillator may be used for instance in a N-PLL-circuit.

公开(公告)号：EP0523854A2

公开(公告)日：1993-01-20

申请号：EP92305478.7

申请日：1992-06-15

Applicant: SGS-Thomson Microelectronics Limited

Inventor： Cytera, Christopher ,  Hall, Andrew Medlicott

IPC: H03L7/099 ,  H03B5/24

CPC classification number: H03L7/0995 ,  H03B5/24 ,  H03B27/00 ,  H03B2200/0038 ,  H03B2200/0058 ,  H03B2200/0062 ,  H03B2200/0078 ,  H03B2201/02 ,  H03L1/00

Abstract: The oscillator comprises a plurality of differential amplication stages (10,12,14,16) each arranged to introduce a phase shift between its differential input signal and its differential output signal such that the total phase shift introduced by the stages is 360 o . In this way an oscillating signal is produced at the output of each stage. Because each stage receives and supplies difference signals, any changes in the power supply of the stages affect both inputs or outputs in the same way so that the effect on the differential signal is minimal. The circuit thus provides a reduction of the effect of power supply noise. The oscillator may be used for instance in a N-PLL-circuit.

Abstract translation: 压控振荡器包括多个差分放大级（10,12,14,16），每个差分放大级被布置成在其差分输入信号与其差分输出信号之间引入相移，使得由级引入的总相位为360°， O>。 以这种方式，在每个级的输出处产生振荡信号。

公开(公告)号：EP0389142A3

公开(公告)日：1992-07-15

申请号：EP90302343.0

申请日：1990-03-06

Applicant: SGS-Thomson Microelectronics Limited

Inventor： Wise, Adrian Philip ,  Forsyth, Richard Matthew

IPC: G11C7/00 ,  G11C11/41 ,  G11C8/00

CPC classification number: G11C11/419 ,  G11C7/10 ,  G11C7/1018

Abstract: A line delay device comprises a memory having RAM cells in two blocks (14,15), each cell being connected to a pair of bit lines. Memory locations in one block (14) are addressed sequentially and subject to a data transfer while an equate operation is effected on the bit lines of the other block (15). The operations are switched alternately between the two blocks (14,15). In each accessing cycle a plurality of locations are addressed in selected rows of each block (14,15) and the switching between each block is effected without addressing all locations in each row addressed so that the accessing cycle ends in a different block (15) from the starting block (14) and each row used has a plurality of addressed locations.