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公开(公告)号：KR1020030025495A
公开(公告)日：2003-03-29
申请号：KR1020010058558
申请日：2001-09-21
Applicant: 삼성전자주식회사
IPC: H01L21/027
Abstract: PURPOSE: A wafer having a primary mark is provided to increase a size of a primary signal induced from the primary mark by increasing a size of a primary mark without reducing an area of a chip. CONSTITUTION: An exposure field(20) is formed with a plurality of chips(21) and a plurality of scribe lanes(22). The scribe lanes(22) are located at edges of the chips(21). A plurality of projection portions(24a,24b) is formed on an edge portion as intersection portions between the scribe lanes located on edges of the exposure field(20). A plurality of primary marks(25a,25b) is located within the scribe lanes(22) including the projection portions(24a,24b). A plurality of recesses(26a,26b) are formed on the scribe lanes corresponding to the scribe lanes(22) having the projection portions(24a,24b) in order to prevent an over-exposure phenomenon of the scribe lanes(22) facing the projection portions(24a,24b).
Abstract translation: 目的：提供具有主标记的晶片，以通过增加初级标记的尺寸来增加从初级标记引起的初级信号的尺寸，而不会减小芯片的面积。 构成：曝光场（20）形成有多个芯片（21）和多个划线（22）。 划线（22）位于芯片（21）的边缘。 多个突出部分（24a，24b）形成在位于曝光区域（20）的边缘上的划线之间的交叉部分的边缘部分上。 多个主标记（25a，25b）位于包括突出部分（24a，24b）的划线（22）内。 为了防止划线路（22）的过度曝光现象面对着该多个凹槽（26a，26b），与划分通道（22）相对应的划线线形成有具有突出部分（24a，24b） 突出部分（24a，24b）。
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公开(公告)号：KR1020010056239A
公开(公告)日：2001-07-04
申请号：KR1019990057624
申请日：1999-12-14
Applicant: 삼성전자주식회사
IPC: H01L21/768
Abstract: PURPOSE: A semiconductor device and a fabrication method thereof are provided to reduce the size of patterns by lowering the stack height of the patterns and securing a more overlay margin. CONSTITUTION: The semiconductor device includes bit lines(200) buried inside a semiconductor substrate by a damascene manner, isolation regions(115) formed to define active areas(150) of the substrate between the bit lines(200), gate lines(600) formed to cross over the active areas(150) and overlap with the bit lines(200), and a storage node(700) formed on the active areas(150) between the gate lines(600). The device may further include bit line contacts(210) connecting the bit lines(200) and the active areas(200). Preferably, the bit lines(200) have a lower level than the substrate in the active areas(150). Therefore, the patterns stacked in layers are reduced in height, and further, the overlay margin in the formation of the storage node(700) is increased since there is no need to consider an overlay with the bit lines(200).
Abstract translation: 目的：提供一种半导体器件及其制造方法，通过降低图案的堆叠高度并确保更多的覆盖边缘来减小图案的尺寸。 构成：半导体器件包括通过镶嵌方式埋在半导体衬底内的位线（200），形成为限定位线（200），栅极线（600）之间的衬底的有源区（150）的隔离区（115） 形成为跨越有源区域（150）并与位线（200）重叠，以及形成在栅极线（600）之间的有源区域（150）上的存储节点（700）。 该装置还可以包括连接位线（200）和有效区域（200）的位线触点（210）。 优选地，位线（200）在有源区域（150）中具有比衬底更低的电平。 因此，堆叠在层中的图案的高度减小，此外，由于不需要考虑与位线（200）的覆盖，因此存储节点（700）的形成中的覆盖边缘增加。
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公开(公告)号：KR1020010055886A
公开(公告)日：2001-07-04
申请号：KR1019990057209
申请日：1999-12-13
Applicant: 삼성전자주식회사
IPC: H01L27/108
Abstract: PURPOSE: A capacitor of a cylinder type and a fabrication method thereof are provided to increase capacitance of the capacitor by enlarging a surface area of a lower electrode. CONSTITUTION: The capacitor includes the cylindrical lower electrode(64) which is formed on an interlayer dielectric layer(42) having a contact hole(44) and also connected to a substrate through a conductive plug(46) filled in the contact hole(44). In particular, the cylindrical lower electrode(64) is composed of a cylindrical outer wall and a plurality of conductive inner walls dividing a space in the cylindrical outer wall. The conductive inner walls increase the entire surface area of the lower electrode(64). In the method, the first insulating layer having a via hole is formed on the interlayer dielectric layer(42). The via hole is greater than the contact hole(44) in the interlayer dielectric layer(42), so that the conductive plug(46) is exposed in the via hole. Next, the first conductive layer to be used as the cylindrical outer wall is formed along entire surfaces, and the second insulating layer dividing the via hole is formed thereon. The second insulating layer is then covered with the second conductive layer to be used as the inner walls. Next, the third insulating layer is formed over an entire structure and then planarized until the first insulating layer is exposed, and all remaining insulating layers are removed.
Abstract translation: 目的：提供一种圆柱型电容器及其制造方法，通过放大下电极的表面积来增加电容器的电容。 构成：电容器包括形成在具有接触孔（44）的层间电介质层（42）上并且还通过填充在接触孔（44）中的导电插塞（46）连接到衬底的圆柱形下电极（64） ）。 特别地，圆筒状的下部电极64由圆筒状的外壁和分割圆筒状的外壁的空间的多个导电内壁构成。 导电内壁增加了下电极（64）的整个表面积。 在该方法中，在层间电介质层（42）上形成具有通孔的第一绝缘层。 通孔大于层间介质层（42）中的接触孔（44），导电插头（46）暴露在通孔中。 接下来，沿着整个表面形成用作圆柱形外壁的第一导电层，并且在其上形成分隔通孔的第二绝缘层。 然后第二绝缘层被第二导电层覆盖以用作内壁。 接下来，在整个结构上形成第三绝缘层，然后平坦化直到第一绝缘层露出，并且除去所有剩余的绝缘层。
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公开(公告)号：KR1020010027865A
公开(公告)日：2001-04-06
申请号：KR1019990039837
申请日：1999-09-16
Applicant: 삼성전자주식회사
IPC: H01L21/283
CPC classification number: H01L21/76897
Abstract: PURPOSE: A method for manufacturing a semiconductor device having a self-aligned contact is provided to increase align margin of a photolithography process by self-aligning a width of a contact formed between a conductive region and a conductive line by a line width of the conductive line. CONSTITUTION: A conductive region(31) is formed on a semiconductor substrate(30). The first interlayer dielectric(32) is formed on the entire semiconductor substrate having the conductive region. A conductive line to be connected to the conductive region is formed on the first interlayer dielectric. The second interlayer dielectric(36) is formed on the conductive line. The first interlayer dielectric, the conductive line and the second interlayer dielectric formed on the conductive region are eliminated to form a contact hole(42) exposing the conductive region. A conductive material is filled in the contact hole to connect the conductive line with the conductive region.
Abstract translation: 目的：提供一种用于制造具有自对准接触的半导体器件的方法，以通过将形成在导电区域和导电线路之间的接触的宽度自身对准导电线的宽度来增加光刻工艺的对准边缘 线。 构成：在半导体衬底（30）上形成导电区域（31）。 第一层间电介质（32）形成在具有导电区域的整个半导体衬底上。 在第一层间电介质上形成与导电区连接的导线。 第二层间电介质（36）形成在导电线上。 消除了形成在导电区域上的第一层间电介质，导电线和第二层间电介质，形成露出导电区域的接触孔（42）。 导电材料填充在接触孔中，以将导电线与导电区域连接起来。
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公开(公告)号：KR1020000012848A
公开(公告)日：2000-03-06
申请号：KR1019980031389
申请日：1998-08-01
Applicant: 삼성전자주식회사
IPC: H01L21/288
Abstract: PURPOSE: A wafer holder of plating apparatus is provided to improve a use efficiency of wafer holder and to improve a capability of plating. CONSTITUTION: The wafer holder comprises a center plate having a safe receipt groove in center of both sides to fix a wafer and an electrode plate on an upper end, two fixing plates hingedly coupled on lower end of the center plate to open and close and having plating groove in center to expose one surface of the wafer, an electrode plates installed on an external surface of each of the fixing plates and for connecting the electrode plate and the wafer, and a fixing plate latch installed on center of an upper surface of the center plate to fix the closed fixing plate.
Abstract translation: 目的：提供电镀装置的晶片保持器，以提高晶片保持器的使用效率并提高电镀能力。 构成：晶片保持架包括中心板，其中心板具有位于两侧中心的安全接收槽，用于将晶片和电极板固定在上端，两个固定板铰接在中心板的下端以打开和关闭并具有 电镀槽在中心以暴露晶片的一个表面，安装在每个固定板的外表面上并用于连接电极板和晶片的电极板，以及安装在该电极板的上表面的中心的固定板闩锁 中心板固定封闭的固定板。
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Patent Agency Ranking
公开(公告)号：KR1020000002395A
公开(公告)日：2000-01-15
申请号：KR1019980023113
申请日：1998-06-19
Applicant: 삼성전자주식회사
Inventor： 박준수
IPC: H03K3/356 , H03K3/0233
Abstract: PURPOSE: A D flip-flop is provided to reduce the lay out area by decreasing the number of gates. CONSTITUTION: D flip flop comprises; the 1st transfer circuit to receive an outside input data; the 1st latch circuit(100) to latch the data transferred thru the above transfer circuit; the 2nd transfer circuit to transfer the data stored in the 1st latch circuit(100) to the next step; the 2nd latch circuit to receive the 1st latch circuit(100) data thru the 2nd transfer circuit and to latch it.
Abstract translation: 目的：提供D触发器，通过减少门数来减少布局面积。 构成：D触发器包括 第一传输电路接收外部输入数据; 第一锁存电路（100）锁存通过上述传送电路传输的数据; 第二传送电路，将存储在第一锁存电路（100）中的数据传送到下一步骤; 第二锁存电路，通过第二传输电路接收第一锁存电路（100）数据并将其锁存。
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公开(公告)号：KR1019980068877A
公开(公告)日：1998-10-26
申请号：KR1019970005672
申请日：1997-02-25
Applicant: 삼성전자주식회사
Inventor： 박준수
IPC: H04N5/72
Abstract: 본발명은 네가티브 블랙 스트립을 적용하되,상기 스트립의 셀수를 늘려 입사되는 광효율을 향상시켜 시야각,콘트 라스트,해상도를 향상시키는 장치를 제공하기위해 렌티 큘러 렌즈를 다수의 반원통형으로 양면으로 양각화되어 형성된 한쪽면의 반원통사이 각홈에 비반사용 흑색잉크를 채워 다수의 네가티브 블랙 스트립셀이 형성되도록 구성되어 있다.
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公开(公告)号：KR1019980043267A
公开(公告)日：1998-09-05
申请号：KR1019960061074
申请日：1996-12-02
Applicant: 삼성전자주식회사
Inventor： 박준수
IPC: H01L21/28
Abstract: 본 발명은 반도체 장치의 금속패턴 형성 방법에 관한 것으로, 반도체 장치의 금속패턴 형성 영역에 이미 설정된 디자인 룰에 따라 소정의 금속패턴 사이의 거리를 갖고, 콘택 또는 비아와 오버랩 되는 소정의 금속패턴 엔드 폭을 갖는 복수의 금속패턴을 디자인하는 제 1 레이아웃 단계와, 복수의 금속패턴의 금속패턴 사이의 거리를 유지하면서, 콘택 또는 비아 영역과 오버랩 되는 금속패턴 엔드 폭을 소정의 금속패턴 엔드 확장 폭만큼 증가시키는 제 2 레이아웃 단계를 포함하여, 반도체 장치의 공정 마진을 증가시킬 수 있고, 수율을 향상시킬 수 있다.
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公开(公告)号：KR2019980009997U
公开(公告)日：1998-04-30
申请号：KR2019960023354
申请日：1996-07-31
Applicant: 삼성전자주식회사
IPC: H04N5/74
Abstract: 프로젝션화상초점조절장치에있어서, 프로젝션TV의렌즈부(102)의빛을직접수광하여반사하는제1밀러(103)에외부초점조절용초점조절장치(100)를설치하여상기프로젝션 TV의외부에설치된상기조절장치(100)의제1노드(209)에의해제1밀러(103)의전체를수평이동토록하고, 제2노브(210)에의해상기제1밀러 (103)의반사각도를미세조정하여빛의초점을조절토록함을특징으로하는장치.
Abstract translation: 在投影图像聚焦装置，其特征在于，通过安装所述外部焦点调整，焦点调整装置100在投影电视意想不到部分提供到第一镜103这反映了直接光接收透镜102 uibit投影电视 控制100议程1和以往节点209被关断第一反射镜103水平地整体的移动到第二旋钮（210）到离岸基反射角的1个镜103也是微调的光的焦点 设备的特征在于它控制如初。
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